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 REJ09B0025-0400
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
16
H8/36024Group, H8/36014Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36024F H8/36022F H8/36014F H8/36012F H8/36024 H8/36023 H8/36022 H8/36014 H8/36013 H8/36012 H8/36011 H8/36010 HD64F36024, HD64F36022, HD64F36014, HD64F36012, HD64336024, HD64336023, HD64336022, HD64336014, HD64336013, HD64336012, HD64336011, HD64336010, HD64F36024G, HD64F36022G, HD64F36014G, HD64F36012G, HD64336024G, HD64336023G, HD64336022G, HD64336014G, HD64336013G, HD64336012G, HD64336011G, HD64336010G
Rev.4.00 Revision Date: Sep. 23, 2005
Rev. 4.00 Sep. 23, 2005 Page ii of xxvi
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 4.00 Sep. 23, 2005 Page iii of xxvi
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 4.00 Sep. 23, 2005 Page iv of xxvi
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 4.00 Sep. 23, 2005 Page v of xxvi
Preface
The H8/36024 Group and H8/36014 Group are single-chip microcomputers made up of the highspeed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36024 Group and H8/36014 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8/36024 Group and H8/36014 Group to the target users. Refer to the H8/300H Series Software Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8/300H Series Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 17, List of Registers. Example: Bit order: The MSB is on the left and the LSB is on the right. Notes: When using the on-chip emulator (E7, E8) for H8/36014 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user. 3. Area H'F780 to H'FB7F must on no account be accessed.
Rev. 4.00 Sep. 23, 2005 Page vi of xxvi
4. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 5. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode). 6. Use channel 1 of the SCI3 (P21/RXD, P22/TXD) in on-board programming mode by boot mode. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
H8/36024 Group and H8/36014 Group manuals:
Document Title H8/36024 Group, H8/36014 Group Hardware Manual H8/300H Series Software Manual Document No. This manual REJ09B0213
User's manuals for development tools:
Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-Performance Embedded Workshop 3, Tutorial H8S, H8/300 Series High-Performance Embedded Workshop 3, User's Manual Document No. REJ10B0058 ADE-702-282 REJ10B0024 REJ10B0026
Application notes:
Document Title H8S, H8/300 Series C/C++ Compiler Package Application Note Single Power Supply F-ZTATTM On-Board Programming Document No. REJ05B0464 ADE-502-055
Rev. 4.00 Sep. 23, 2005 Page vii of xxvi
Rev. 4.00 Sep. 23, 2005 Page viii of xxvi
Contents
Section 1 Overview................................................................................................1
1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 3 Pin Arrangement .................................................................................................................... 4 Pin Functions ......................................................................................................................... 6
Section 2 CPU........................................................................................................9
2.1 2.2 Address Space and Memory Map ........................................................................................ 10 Register Configuration......................................................................................................... 12 2.2.1 General Registers.................................................................................................... 13 2.2.2 Program Counter (PC) ............................................................................................ 14 2.2.3 Condition-Code Register (CCR)............................................................................. 14 Data Formats........................................................................................................................ 16 2.3.1 General Register Data Formats ............................................................................... 16 2.3.2 Memory Data Formats ............................................................................................ 18 Instruction Set ...................................................................................................................... 19 2.4.1 Table of Instructions Classified by Function .......................................................... 19 2.4.2 Basic Instruction Formats ....................................................................................... 28 Addressing Modes and Effective Address Calculation........................................................ 30 2.5.1 Addressing Modes .................................................................................................. 30 2.5.2 Effective Address Calculation ................................................................................ 33 Basic Bus Cycle ................................................................................................................... 35 2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 35 2.6.2 On-Chip Peripheral Modules .................................................................................. 36 CPU States ........................................................................................................................... 37 Usage Notes ......................................................................................................................... 38 2.8.1 Notes on Data Access to Empty Areas ................................................................... 38 2.8.2 EEPMOV Instruction.............................................................................................. 38 2.8.3 Bit Manipulation Instruction................................................................................... 38
2.3
2.4
2.5
2.6
2.7 2.8
Section 3 Exception Handling .............................................................................45
3.1 3.2 Exception Sources and Vector Address ............................................................................... 45 Register Descriptions ........................................................................................................... 47 3.2.1 Interrupt Edge Select Register 1 (IEGR1) .............................................................. 47 3.2.2 Interrupt Edge Select Register 2 (IEGR2) .............................................................. 48 3.2.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 49
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3.3 3.4
3.5
3.2.4 Interrupt Flag Register 1 (IRR1)............................................................................. 50 3.2.5 Wakeup Interrupt Flag Register (IWPR) ................................................................ 51 Reset Exception Handling.................................................................................................... 52 Interrupt Exception Handling .............................................................................................. 53 3.4.1 External Interrupts .................................................................................................. 53 3.4.2 Internal Interrupts ................................................................................................... 54 3.4.3 Interrupt Handling Sequence .................................................................................. 55 3.4.4 Interrupt Response Time......................................................................................... 56 Usage Notes ......................................................................................................................... 58 3.5.1 Interrupts after Reset............................................................................................... 58 3.5.2 Notes on Stack Area Use ........................................................................................ 58 3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 58
Section 4 Address Break ..................................................................................... 59
4.1 Register Descriptions........................................................................................................... 59 4.1.1 Address Break Control Register (ABRKCR) ......................................................... 60 4.1.2 Address Break Status Register (ABRKSR) ............................................................ 61 4.1.3 Break Address Registers (BARH, BARL).............................................................. 62 4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 62 Operation ............................................................................................................................. 62
4.2
Section 5 Clock Pulse Generators ....................................................................... 65
5.1 System Clock Generator ...................................................................................................... 65 5.1.1 Connecting Crystal Resonator ................................................................................ 66 5.1.2 Connecting Ceramic Resonator .............................................................................. 66 5.1.3 External Clock Input Method ................................................................................. 67 Prescalers ............................................................................................................................. 67 5.2.1 Prescaler S .............................................................................................................. 67 Usage Notes ......................................................................................................................... 67 5.3.1 Note on Resonators................................................................................................. 67 5.3.2 Notes on Board Design ........................................................................................... 68
5.2 5.3
Section 6 Power-Down Modes............................................................................ 69
6.1 Register Descriptions........................................................................................................... 69 6.1.1 System Control Register 1 (SYSCR1) .................................................................... 70 6.1.2 System Control Register 2 (SYSCR2) .................................................................... 71 6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 72 6.1.4 Module Standby Control Register 2 (MSTCR2) .................................................... 72 Mode Transitions and States of LSI..................................................................................... 73 6.2.1 Sleep Mode ............................................................................................................. 75
6.2
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6.3 6.4 6.5
6.2.2 Standby Mode ......................................................................................................... 75 6.2.3 Subsleep Mode........................................................................................................ 75 Operating Frequency in Active Mode.................................................................................. 76 Direct Transition .................................................................................................................. 76 Module Standby Function.................................................................................................... 76
Section 7 ROM ....................................................................................................77
7.1 7.2 Block Configuration............................................................................................................. 78 Register Descriptions ........................................................................................................... 79 7.2.1 Flash Memory Control Register 1 (FLMCR1)........................................................ 79 7.2.2 Flash Memory Control Register 2 (FLMCR2)........................................................ 80 7.2.3 Erase Block Register 1 (EBR1) .............................................................................. 81 7.2.4 Flash Memory Enable Register (FENR) ................................................................. 81 On-Board Programming Modes........................................................................................... 82 7.3.1 Boot Mode .............................................................................................................. 82 7.3.2 Programming/Erasing in User Program Mode........................................................ 85 Flash Memory Programming/Erasing .................................................................................. 86 7.4.1 Program/Program-Verify ........................................................................................ 86 7.4.2 Erase/Erase-Verify.................................................................................................. 88 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory............................. 89 Program/Erase Protection .................................................................................................... 91 7.5.1 Hardware Protection ............................................................................................... 91 7.5.2 Software Protection................................................................................................. 91 7.5.3 Error Protection....................................................................................................... 91
7.3
7.4
7.5
Section 8 RAM ....................................................................................................93 Section 9 I/O Ports ...............................................................................................95
9.1 Port 1.................................................................................................................................... 95 9.1.1 Port Mode Register 1 (PMR1) ................................................................................ 96 9.1.2 Port Control Register 1 (PCR1) .............................................................................. 97 9.1.3 Port Data Register 1 (PDR1)................................................................................... 97 9.1.4 Port Pull-Up Control Register 1 (PUCR1).............................................................. 98 9.1.5 Pin Functions .......................................................................................................... 98 Port 2.................................................................................................................................. 100 9.2.1 Port Control Register 2 (PCR2) ............................................................................ 100 9.2.2 Port Data Register 2 (PDR2)................................................................................. 101 9.2.3 Pin Functions ........................................................................................................ 101 Port 5.................................................................................................................................. 102 9.3.1 Port Mode Register 5 (PMR5) .............................................................................. 103
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9.2
9.3
9.4
9.5
9.6
9.3.2 Port Control Register 5 (PCR5) ............................................................................ 104 9.3.3 Port Data Register 5 (PDR5) ................................................................................ 105 9.3.4 Port Pull-Up Control Register 5 (PUCR5)............................................................ 105 9.3.5 Pin Functions ........................................................................................................ 106 Port 7.................................................................................................................................. 108 9.4.1 Port Control Register 7 (PCR7) ............................................................................ 109 9.4.2 Port Data Register 7 (PDR7) ................................................................................ 109 9.4.3 Pin Functions ........................................................................................................ 110 Port 8.................................................................................................................................. 112 9.5.1 Port Control Register 8 (PCR8) ............................................................................ 112 9.5.2 Port Data Register 8 (PDR8) ................................................................................ 113 9.5.3 Pin Functions ........................................................................................................ 113 Port B ................................................................................................................................. 115 9.6.1 Port Data Register B (PDRB) ............................................................................... 116
Section 10 Timer V ........................................................................................... 117
10.1 Features.............................................................................................................................. 117 10.2 Input/Output Pins............................................................................................................... 119 10.3 Register Descriptions......................................................................................................... 119 10.3.1 Timer Counter V (TCNTV).................................................................................. 119 10.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 120 10.3.3 Timer Control Register V0 (TCRV0) ................................................................... 121 10.3.4 Timer Control/Status Register V (TCSRV) .......................................................... 123 10.3.5 Timer Control Register V1 (TCRV1) ................................................................... 125 10.4 Operation ........................................................................................................................... 126 10.4.1 Timer V Operation................................................................................................ 126 10.5 Timer V Application Examples ......................................................................................... 130 10.5.1 Pulse Output with Arbitrary Duty Cycle............................................................... 130 10.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .............. 131 10.6 Usage Notes ....................................................................................................................... 132
Section 11 Timer W........................................................................................... 135
11.1 Features.............................................................................................................................. 135 11.2 Input/Output Pins............................................................................................................... 138 11.3 Register Descriptions......................................................................................................... 138 11.3.1 Timer Mode Register W (TMRW) ....................................................................... 139 11.3.2 Timer Control Register W (TCRW) ..................................................................... 140 11.3.3 Timer Interrupt Enable Register W (TIERW) ...................................................... 141 11.3.4 Timer Status Register W (TSRW) ........................................................................ 142 11.3.5 Timer I/O Control Register 0 (TIOR0) ................................................................. 144
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11.3.6 Timer I/O Control Register 1 (TIOR1) ................................................................. 145 11.3.7 Timer Counter (TCNT)......................................................................................... 147 11.3.8 General Registers A to D (GRA to GRD)............................................................. 147 11.4 Operation ........................................................................................................................... 148 11.4.1 Normal Operation ................................................................................................. 148 11.4.2 PWM Operation.................................................................................................... 153 11.5 Operation Timing............................................................................................................... 158 11.5.1 TCNT Count Timing ............................................................................................ 158 11.5.2 Output Compare Output Timing ........................................................................... 159 11.5.3 Input Capture Timing............................................................................................ 160 11.5.4 Timing of Counter Clearing by Compare Match .................................................. 160 11.5.5 Buffer Operation Timing ...................................................................................... 161 11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match.................................. 161 11.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................. 162 11.5.8 Timing of Status Flag Clearing............................................................................. 163 11.6 Usage Notes ....................................................................................................................... 163
Section 12 Watchdog Timer ..............................................................................167
12.1 Features.............................................................................................................................. 167 12.2 Register Descriptions ......................................................................................................... 168 12.2.1 Timer Control/Status Register WD (TCSRWD)................................................... 168 12.2.2 Timer Counter WD (TCWD)................................................................................ 169 12.2.3 Timer Mode Register WD (TMWD) .................................................................... 170 12.3 Operation ........................................................................................................................... 171
Section 13 Serial Communication Interface 3 (SCI3) .......................................173
13.1 Features.............................................................................................................................. 173 13.2 Input/Output Pins ............................................................................................................... 177 13.3 Register Descriptions ......................................................................................................... 177 13.3.1 Receive Shift Register (RSR) ............................................................................... 178 13.3.2 Receive Data Register (RDR) ............................................................................... 178 13.3.3 Transmit Shift Register (TSR) .............................................................................. 178 13.3.4 Transmit Data Register (TDR).............................................................................. 178 13.3.5 Serial Mode Register (SMR) ................................................................................ 179 13.3.6 Serial Control Register 3 (SCR3).......................................................................... 180 13.3.7 Serial Status Register (SSR) ................................................................................. 182 13.3.8 Bit Rate Register (BRR) ....................................................................................... 184 13.3.9 SCI3_3 Module Control Register (SMCR)........................................................... 191 13.4 Operation in Asynchronous Mode ..................................................................................... 192 13.4.1 Clock..................................................................................................................... 192
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13.5
13.6
13.7 13.8
13.4.2 SCI3 Initialization................................................................................................. 193 13.4.3 Data Transmission ................................................................................................ 194 13.4.4 Serial Data Reception ........................................................................................... 196 Operation in Clocked Synchronous Mode ......................................................................... 200 13.5.1 Clock..................................................................................................................... 200 13.5.2 SCI3 Initialization................................................................................................. 201 13.5.3 Serial Data Transmission ...................................................................................... 201 13.5.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 203 13.5.5 Simultaneous Serial Data Transmission and Reception........................................ 205 Multiprocessor Communication Function.......................................................................... 207 13.6.1 Multiprocessor Serial Data Transmission ............................................................. 208 13.6.2 Multiprocessor Serial Data Reception .................................................................. 210 Interrupts............................................................................................................................ 214 Usage Notes ....................................................................................................................... 215 13.8.1 Break Detection and Processing ........................................................................... 215 13.8.2 Mark State and Break Sending ............................................................................. 215 13.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 215 13.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode..................................................................................................................... 216
Section 14 A/D Converter ................................................................................. 217
14.1 Features.............................................................................................................................. 217 14.2 Input/Output Pins............................................................................................................... 219 14.3 Register Description .......................................................................................................... 220 14.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 220 14.3.2 A/D Control/Status Register (ADCSR) ................................................................ 221 14.3.3 A/D Control Register (ADCR) ............................................................................. 222 14.4 Operation ........................................................................................................................... 223 14.4.1 Single Mode.......................................................................................................... 223 14.4.2 Scan Mode ............................................................................................................ 223 14.4.3 Input Sampling and A/D Conversion Time .......................................................... 224 14.4.4 External Trigger Input Timing.............................................................................. 225 14.5 A/D Conversion Accuracy Definitions .............................................................................. 226 14.6 Usage Notes ....................................................................................................................... 228 14.6.1 Permissible Signal Source Impedance .................................................................. 228 14.6.2 Influences on Absolute Accuracy ......................................................................... 228
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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional).........................................................................................229
15.1 Features.............................................................................................................................. 229 15.2 Register Descriptions ......................................................................................................... 230 15.2.1 Low-Voltage-Detection Control Register (LVDCR)............................................ 231 15.2.2 Low-Voltage-Detection Status Register (LVDSR)............................................... 232 15.3 Operation ........................................................................................................................... 233 15.3.1 Power-On Reset Circuit ........................................................................................ 233 15.3.2 Low-Voltage Detection Circuit............................................................................. 234
Section 16 Power Supply Circuit.......................................................................237
16.1 When Using Internal Power Supply Step-Down Circuit.................................................... 237 16.2 When Not Using Internal Power Supply Step-Down Circuit............................................. 238
Section 17 List of Registers ...............................................................................225
17.1 Register Addresses (Address Order).................................................................................. 226 17.2 Register Bits....................................................................................................................... 230 17.3 Register States in Each Operating Mode ........................................................................... 233
Section 18 Electrical Characteristics .................................................................251
18.1 Absolute Maximum Ratings .............................................................................................. 251 18.2 Electrical Characteristics (F-ZTATTM Version).................................................................. 251 18.2.1 Power Supply Voltage and Operating Ranges ...................................................... 251 18.2.2 DC Characteristics ................................................................................................ 254 18.2.3 AC Characteristics ................................................................................................ 259 18.2.4 A/D Converter Characteristics .............................................................................. 262 18.2.5 Watchdog Timer Characteristics........................................................................... 263 18.2.6 Flash Memory Characteristics .............................................................................. 264 18.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ................... 266 18.2.8 Power-On Reset Circuit Characteristics (Optional) .............................................. 267 18.3 Electrical Characteristics (Masked ROM Version)............................................................ 267 18.3.1 Power Supply Voltage and Operating Ranges ...................................................... 267 18.3.2 DC Characteristics ................................................................................................ 270 18.3.3 AC Characteristics ................................................................................................ 275 18.3.4 A/D Converter Characteristics .............................................................................. 278 18.3.5 Watchdog Timer Characteristics........................................................................... 279 18.3.6 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ................... 280 18.3.7 Power-On Reset Circuit Characteristics (Optional) .............................................. 281 18.4 Operation Timing............................................................................................................... 281
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18.5 Output Load Condition ...................................................................................................... 283
Appendix A Instruction Set ............................................................................... 285
A.1 A.2 A.3 A.4 Instruction List................................................................................................................... 285 Operation Code Map.......................................................................................................... 300 Number of Execution States .............................................................................................. 303 Combinations of Instructions and Addressing Modes ....................................................... 314
Appendix B I/O Port Block Diagrams............................................................... 315
B.1 B.2 I/O Port Block Diagrams ................................................................................................... 315 Port States in Each Operating State ................................................................................... 337
Appendix C Product Code Lineup .................................................................... 338 Appendix D Package Dimensions ..................................................................... 342 Main Revisions and Additions in this Edition..................................................... 347 Index ......................................................................................................... 351
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Figures
Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Overview Internal Block Diagram ................................................................................................. 3 Pin Arrangement (FP-64E)............................................................................................ 4 Pin Arrangement (FP-48F, FP-48B, TNP-48)............................................................... 5
Section 2 CPU Figure 2.1 Memory Map (1) ......................................................................................................... 10 Figure 2.1 Memory Map (2) ......................................................................................................... 11 Figure 2.2 CPU Registers ............................................................................................................. 12 Figure 2.3 Usage of General Registers ......................................................................................... 13 Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 14 Figure 2.5 General Register Data Formats (1).............................................................................. 16 Figure 2.5 General Register Data Formats (2).............................................................................. 17 Figure 2.6 Memory Data Formats................................................................................................. 18 Figure 2.7 Instruction Formats...................................................................................................... 29 Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 33 Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 35 Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 36 Figure 2.11 CPU Operation States................................................................................................ 37 Figure 2.12 State Transitions ........................................................................................................ 38 Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address...................................................................................................................... 39 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Section 4 Figure 4.1 Figure 4.2 Figure 4.2 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Exception Handling Reset Sequence............................................................................................................ 54 Stack Status after Exception Handling ........................................................................ 56 Interrupt Sequence....................................................................................................... 57 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 58 Address Break Block Diagram of Address Break................................................................................ 59 Address Break Interrupt Operation Example (1)......................................................... 63 Address Break Interrupt Operation Example (2)......................................................... 63 Clock Pulse Generators Block Diagram of Clock Pulse Generators.................................................................. 65 Block Diagram of System Clock Generator ................................................................ 65 Typical Connection to Crystal Resonator.................................................................... 66 Equivalent Circuit of Crystal Resonator...................................................................... 66
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Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 66 Figure 5.6 Example of External Clock Input ................................................................................ 67 Figure 5.7 Example of Incorrect Board Design ............................................................................ 68 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ........................................................................................... 73 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 ROM Flash Memory Block Configuration............................................................................. 78 Programming/Erasing Flowchart Example in User Program Mode............................ 85 Program/Program-Verify Flowchart ............................................................................ 87 Erase/Erase-Verify Flowchart ..................................................................................... 90 I/O Ports Port 1 Pin Configuration.............................................................................................. 95 Port 2 Pin Configuration............................................................................................ 100 Port 5 Pin Configuration............................................................................................ 102 Port 7 Pin Configuration............................................................................................ 108 Port 8 Pin Configuration............................................................................................ 112 Port B Pin Configuration........................................................................................... 115
Section 10 Timer V Figure 10.1 Block Diagram of Timer V ..................................................................................... 118 Figure 10.2 Increment Timing with Internal Clock .................................................................... 127 Figure 10.3 Increment Timing with External Clock................................................................... 127 Figure 10.4 OVF Set Timing ...................................................................................................... 127 Figure 10.5 CMFA and CMFB Set Timing................................................................................ 128 Figure 10.6 TMOV Output Timing ............................................................................................ 128 Figure 10.7 Clear Timing by Compare Match............................................................................ 128 Figure 10.8 Clear Timing by TMRIV Input ............................................................................... 129 Figure 10.9 Pulse Output Example ............................................................................................. 130 Figure 10.10 Example of Pulse Output Synchronized to TRGV Input....................................... 131 Figure 10.11 Contention between TCNTV Write and Clear ...................................................... 132 Figure 10.12 Contention between TCORA Write and Compare Match ..................................... 133 Figure 10.13 Internal Clock Switching and TCNTV Operation ................................................. 133 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Timer W Timer W Block Diagram......................................................................................... 137 Free-Running Counter Operation ............................................................................ 148 Periodic Counter Operation..................................................................................... 149 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 149 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 150 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 150
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Figure 11.7 Input Capture Operating Example........................................................................... 151 Figure 11.8 Buffer Operation Example (Input Capture)............................................................. 152 Figure 11.9 PWM Mode Example (1) ........................................................................................ 153 Figure 11.10 PWM Mode Example (2) ...................................................................................... 154 Figure 11.11 Buffer Operation Example (Output Compare) ...................................................... 155 Figure 11.12 PWM Mode Example (TOB, TOC, and TOD = 0: initial output values are set to 0) ............................... 156 Figure 11.13 PWM Mode Example (TOB, TOC, and TOD = 1: initial output values are set to 1) ............................... 157 Figure 11.14 Count Timing for Internal Clock Source ............................................................... 158 Figure 11.15 Count Timing for External Clock Source.............................................................. 158 Figure 11.16 Output Compare Output Timing ........................................................................... 159 Figure 11.17 Input Capture Input Signal Timing........................................................................ 160 Figure 11.18 Timing of Counter Clearing by Compare Match................................................... 160 Figure 11.19 Buffer Operation Timing (Compare Match).......................................................... 161 Figure 11.20 Buffer Operation Timing (Input Capture) ............................................................. 161 Figure 11.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 162 Figure 11.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 162 Figure 11.23 Timing of Status Flag Clearing by CPU................................................................ 163 Figure 11.24 Contention between TCNT Write and Clear ......................................................... 164 Figure 11.25 Internal Clock Switching and TCNT Operation.................................................... 164 Figure 11.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing ......................................................................................................... 165 Section 12 Watchdog Timer Figure 12.1 Block Diagram of Watchdog Timer ........................................................................ 167 Figure 12.2 Watchdog Timer Operation Example...................................................................... 171 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.8 Serial Communication Interface 3 (SCI3) Block Diagram of SCI3 ........................................................................................... 176 Data Format in Asynchronous Communication ...................................................... 192 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits) .............. 192 Sample SCI3 Initialization Flowchart ..................................................................... 193 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 194 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 195 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 196 Sample Serial Reception Data Flowchart (Asynchronous Mode)(1)....................... 198 Sample Serial Reception Data Flowchart (Asynchronous Mode)(2)....................... 199
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Figure 13.9 Data Format in Clocked Synchronous Communication .......................................... 200 Figure 13.10 Example of SCI3 Transmission in Clocked Synchronous Mode .......................... 202 Figure 13.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 202 Figure 13.12 Example of SCI3 Reception in Clocked Synchronous Mode................................ 203 Figure 13.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 204 Figure 13.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)............................................................................... 206 Figure 13.15 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) .......................................... 208 Figure 13.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 209 Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 211 Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 212 Figure 13.18 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 213 Figure 13.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 216 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 A/D Converter Block Diagram of A/D Converter ........................................................................... 218 A/D Conversion Timing.......................................................................................... 224 External Trigger Input Timing ................................................................................ 225 A/D Conversion Accuracy Definitions (1).............................................................. 227 A/D Conversion Accuracy Definitions (2).............................................................. 227 Analog Input Circuit Example ................................................................................ 228 Power-On Reset and Low-Voltage Detection Circuits (Optional) Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 230 Operational Timing of Power-On Reset Circuit...................................................... 233 Operational Timing of LVDR Circuit ..................................................................... 234 Operational Timing of LVDI Circuit ...................................................................... 235 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 236
Section 16 Power Supply Circuit Figure 16.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 237 Figure 16.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 238 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Electrical Characteristics System Clock Input Timing .................................................................................... 281 RES Low Width Timing.......................................................................................... 282 Input Timing............................................................................................................ 282 SCK3 Input Clock Timing ...................................................................................... 282 SCI3 Input/Output Timing in Clocked Synchronous Mode .................................... 283 Output Load Circuit ................................................................................................ 283
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Appendix Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 315 Figure B.2 Port 1 Block Diagram (P14) ..................................................................................... 316 Figure B.3 Port 1 Block Diagram (P16, P15, P12, P10)............................................................. 317 Figure B.4 Port 1 Block Diagram (P12) (H8/36024).................................................................. 318 Figure B.5 Port 1 Block Diagram (P11) ...................................................................................... 319 Figure B.6 Port 2 Block Diagram (P22) ..................................................................................... 320 Figure B.7 Port 2 Block Diagram (P21) ..................................................................................... 321 Figure B.8 Port 2 Block Diagram (P20) ..................................................................................... 322 Figure B.9 Port 5 Block Diagram (P57, P56) (H8/36014).......................................................... 323 Figure B.10 Port 5 Block Diagram (P57) (H8/36024)................................................................ 324 Figure B.11 Port 5 Block Diagram (P56) (H8/36024)................................................................ 325 Figure B.12 Port 5 Block Diagram (P55) ................................................................................... 326 Figure B.13 Port 5 Block Diagram (P54 to P50) ........................................................................ 327 Figure B.14 Port 7 Block Diagram (P76) ................................................................................... 328 Figure B.15 Port 7 Block Diagram (P75) ................................................................................... 329 Figure B.16 Port 7 Block Diagram (P74) ................................................................................... 330 Figure B.17 Port 7 Block Diagram (P73) ................................................................................... 331 Figure B.18 Port 7 Block Diagram (P72) ................................................................................... 332 Figure B.19 Port 7 Block Diagram (P71) ................................................................................... 333 Figure B.20 Port 7 Block Diagram (P70) ................................................................................... 334 Figure B.21 Port 8 Block Diagram (P84 to P81) ........................................................................ 335 Figure B.22 Port 8 Block Diagram (P80) ................................................................................... 336 Figure B.23 Port B Block Diagram (PB3 to PB0) ...................................................................... 337 Figure D.1 FP-64E Package Dimensions.................................................................................... 343 Figure D.2 FP-48F Package Dimensions.................................................................................... 344 Figure D.3 FP-48B Package Dimensions ................................................................................... 345 Figure D.4 TNP-48 Package Dimensions................................................................................... 346
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Tables
Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 6 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 19 Table 2.2 Data Transfer Instructions....................................................................................... 20 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 21 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 22 Table 2.4 Logic Operations Instructions................................................................................. 22 Table 2.5 Shift Instructions..................................................................................................... 23 Table 2.6 Bit Manipulation Instructions (1)............................................................................ 24 Table 2.6 Bit Manipulation Instructions (2)............................................................................ 25 Table 2.7 Branch Instructions ................................................................................................. 26 Table 2.8 System Control Instructions.................................................................................... 27 Table 2.9 Block Data Transfer Instructions ............................................................................ 28 Table 2.10 Addressing Modes .................................................................................................. 30 Table 2.11 Absolute Address Access Ranges ........................................................................... 32 Table 2.12 Effective Address Calculation (1)........................................................................... 33 Table 2.12 Effective Address Calculation (2)........................................................................... 34 Section 3 Exception Handling Table 3.1 Exception Sources and Vector Address .................................................................. 45 Table 3.2 Interrupt Wait States ............................................................................................... 56 Section 4 Address Break Table 4.1 Access and Data Bus Used ..................................................................................... 61 Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters ................................................................................. 66 Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time................................................................. 70 Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 74 Table 6.3 Internal State in Each Operating Mode................................................................... 74 Section 7 ROM Table 7.1 Setting Programming Modes .................................................................................. 82 Table 7.2 Boot Mode Operation ............................................................................................. 84 Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ................................................................................................................... 85
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Table 7.4 Table 7.5 Table 7.6
Reprogram Data Computation Table ...................................................................... 88 Additional-Program Data Computation Table ........................................................ 88 Programming Time ................................................................................................. 88
Section 10 Timer V Table 10.1 Pin Configuration.................................................................................................. 119 Table 10.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 122 Section 11 Timer W Table 11.1 Timer W Functions ............................................................................................... 136 Table 11.2 Pin Configuration.................................................................................................. 138 Section 13 Serial Communication Interface 3 (SCI3) Table 13.1 Channel Configuration.......................................................................................... 175 Table 13.2 Pin Configuration.................................................................................................. 177 Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 185 Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 186 Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 187 Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 188 Table 13.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) ......................................................................................................................... 189 Table 13.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) ......................................................................................................................... 190 Table 13.6 SSR Status Flags and Receive Data Handling ...................................................... 197 Table 13.7 SCI3 Interrupt Requests........................................................................................ 214 Section 14 A/D Converter Table 14.1 Pin Configuration.................................................................................................. 219 Table 14.2 Analog Input Channels and Corresponding ADDR Registers .............................. 220 Table 14.3 A/D Conversion Time (Single Mode)................................................................... 225 Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 15.1 LVDCR Settings and Select Functions................................................................. 232 Section 18 Electrical Characteristics Table 18.1 Absolute Maximum Ratings ................................................................................. 251 Table 18.2 DC Characteristics (1) .......................................................................................... 254 Table 18.2 DC Characteristics (2) .......................................................................................... 258 Table 18.3 AC Characteristics ................................................................................................ 259 Table 18.4 Serial Interface (SCI3) Timing ............................................................................. 261 Table 18.5 A/D Converter Characteristics.............................................................................. 262 Table 18.6 Watchdog Timer Characteristics........................................................................... 263 Table 18.7 Flash Memory Characteristics .............................................................................. 264
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Table 18.8 Table 18.9 Table 18.10 Table 18.10 Table 18.11 Table 18.12 Table 18.13 Table 18.14 Table 18.15 Table 18.16 Appendix Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5
Power-Supply-Voltage Detection Circuit Characteristics..................................... 266 Power-On Reset Circuit Characteristics................................................................ 267 DC Characteristics (1)....................................................................................... 270 DC Characteristics (2)....................................................................................... 274 AC Characteristics ............................................................................................ 275 Serial Interface (SCI3) Timing ......................................................................... 277 A/D Converter Characteristics .......................................................................... 278 Watchdog Timer Characteristics....................................................................... 279 Power-Supply-Voltage Detection Circuit Characteristics................................. 280 Power-On Reset Circuit Characteristics............................................................ 281 Instruction Set ....................................................................................................... 287 Operation Code Map (1) ....................................................................................... 300 Operation Code Map (2) ....................................................................................... 301 Operation Code Map (3) ....................................................................................... 302 Number of Cycles in Each Instruction.................................................................. 304 Number of Cycles in Each Instruction.................................................................. 305 Combinations of Instructions and Addressing Modes .......................................... 314
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Section 1 Overview
Section 1 Overview
1.1 Features
* High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions * Various peripheral functions Timer V (8-bit timer) Timer W (16-bit timer) Watchdog timer SCI3 (Asynchronous or clocked synchronous serial communication interface) 10-bit A/D converter * On-chip memory
Model On-Chip PowerOn Reset and Low-Voltage Detecting Circuit Version ROM HD64F36024G HD64F36022G HD64F36014G HD64F36012G HD64336024G HD64336023G HD64336022G HD64336014G HD64336013G HD64336012G HD64336011G HD64336010G 32 kbytes 16 kbytes 32 kbytes 16 kbytes 32 kbytes 24 kbytes 16 kbytes 32 kbytes 24 kbytes 16 kbytes 12 kbytes 8 kbytes
Product Classification Flash memory version (F-ZTAT version)
TM
Standard Version HD64F36024 HD64F36022 HD64F36014 HD64F36012 HD64336024 HD64336023 HD64336022 HD64336014 HD64336013 HD64336012 HD64336011 HD64336010
RAM 2,048 bytes 2,048 bytes 2,048 bytes 2,048 bytes 1,024 bytes 1,024 bytes 512 bytes 1,024 bytes 1,024 bytes 512 bytes 512 bytes 512 bytes
H8/36024F H8/36022F H8/36014F H8/36012F
Masked ROM version
H8/36024 H8/36023 H8/36022 H8/36014 H8/36013 H8/36012 H8/36011 H8/36010
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Section 1 Overview
* General I/O ports I/O pins: 30 I/O pins, including 5 large current ports (IOL = 20 mA, @VOL = 1.5 V) Input-only pins: 4 input pins (also used for analog input) * Supports various power-down modes Note: F-ZTATTM is a trademark of Renesas Technology Corp. * Compact package
Package LQFP-64 LQFP-48 LQFP-48 QFN-48 Code FP-64E FP-48F FP-48B TNP-48 Body Size 10.0 x 10.0 mm 7.0 x 7.0 mm 7.0 x 7.0 mm 10.0 x 10.0 mm Pin Pitch 0.5 mm 0.65 mm 0.5 mm 0.5 mm
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Section 1 Overview
1.2
VCC VSS VCL
Internal Block Diagram
OSC1 OSC2
TEST
RES
NMI
Data bus (upper)
System clock generator
CPU H8/300H
Address bus
E10T_0*3 E10T_1*3 E10T_2*3
P17/IRQ3/TRGV P16 P15 P14/IRQ0 P12/SCK3_3*2 P11 P10
P22/TXD P21/RXD P20/SCK3
Data bus (lower)
Port 1
RAM ROM
Port 2
SCI3
P76/TMOV P75/TMCIV P74/TMRIV P73 P72/TXD_2 P71/RXD_2 P70/SCK3_2
CMOS large current port IOL = 20 mA @ VOL = 1.5 V
Timer W
SCI3_2
Timer V
SCI3_3*1
P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI
P57/TXD_3*2 P56/RXD_3*2 P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0
A/D converter
Port 5
Watchdog timer
Port B
PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0
AVCC
Notes: 1. The SCI3_3 function is incorporated in the H8/36024. 2. Since the SCI3_3 function is not incorporated in the H8/36014, the SCK3_3, RXD_3, and TXD_3 pins are not multiplexed. 3. Can also be used for the E7 or E8 emulator.
Figure 1.1 Internal Block Diagram
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Port 8
Port 7
Section 1 Overview
1.3
Pin Arrangement
P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P20/SCK3 E10T_2*2 E10T_1*2 E10T_0*2 P80/FTCI P21/RXD P22/TXD
NMI
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC NC P14/IRQ0 P15 P16 P17/IRQ3/TRGV P73 P72/TXD_2 P71/RXD_2 P70/SCK3_2 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 NC NC
NC
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 34 56 7 8 9 10 11 12 13 14 15 16
H8/36024 Group H8/36014 Group Top view
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
NC NC P76/TMOV P75/TMCIV P74/TMRIV P57/TXD_3*1 P56/RXD_3*1 P12/SCK3_3*1 P11 P10 P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 NC NC
NC
TEST
AVCC
VSS
NC
NC
NC
NC
VCC
P50/WKP0
Notes: Do not connect NC pins (these pins are not connected to the internal circuitry). *1 The SCK3_3, RXD_3, and TXD_3 pins are not multiplexed in the H8/36014. *2 Can also be used for the E7 or E8 emulator.
Figure 1.2 Pin Arrangement (FP-64E)
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P51/WKP1
VCL
RES
OSC2
OSC1
NC
Section 1 Overview
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P20/SCK3
E10T_2*2
E10T_1*2
E10T_0*2
P80/FTCI
P21/RXD
P22/TXD
36 35 34 33 32 31 30 29 28 27 26 25 P14/IRQ0 P15 P16 P17/IRQ3/TRGV P73 P72/TXD_2 P71/RXD_2 P70/SCK3_2 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12
H8/36014 Top view
NMI
24 23 22 21 20 19 18 17 16 15 14 13
P76/TMOV P75/TMCIV P74/TMRIV
P57/TXD_3*1 P56/RXD_3*1 P12/SCK3_3*1
P11 P10 P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2
AVcc
NC
NC
RES
Vss
Vcc
P50/WKP0
Notes: Do not connect NC pins (these pins are not connected to the internal circuitry). *1 The SCK3_3, RXD_3, and TXD_3 pins are not multiplexed in the H8/36014. *2 Can also be used for the E7 or E8 emulator.
Figure 1.3 Pin Arrangement (FP-48F, FP-48B, TNP-48)
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P51/WKP1
TEST
OSC2
OSC1
VCL
Section 1 Overview
1.4
Table 1.1
Pin Functions
Pin Functions
Pin No. FP-48F, FP-48B, TNP-48 10 7 1
Type Power source pins
Symbol VCC VSS AVCC
FP-64E 12 9 3
I/O Input Input Input
Functions Power supply pin. Connect this pin to the system power supply. Ground pin. Connect this pin to the system power supply (0V). Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. Internal step-down power supply pin. Connect a capacitor of around 0.1 F between this pin and the Vss pin for stabilization. These pins connect to a crystal or ceramic resonator for system clocks, or can be used to input an external clock. See section 5, Clock Pulse Generators, for a typical connection.
VCL
6
4
Input
Clock pins
OSC1 OSC2
11 10
9 8
Input Output
System control
RES
7
5
Input
Reset pin. The pull-up resistor (typ. 150 k) is incorporated. When driven low, the chip is reset. Test pin. Connect this pin to Vss. Non-maskable interrupt request input pin. Be sure to pull-up by a pull-up resistor. External interrupt request input pins. Can select the rising or falling edge. External interrupt request input pins. Can select the rising or falling edge.
TEST Interrupt pins NMI
8 35
6 25
Input Input
IRQ0, IRQ3 WKP0 to WKP5
51, 54
37, 40
Input
13, 14, 19 to 22
11 to 16
Input
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Section 1 Overview
Pin No. FP-48F, FP-48B, TNP-48 24
Type Timer V
Symbol TMOV
FP-64E 30
I/O Output
Functions This is an output pin for waveforms generated by the output compare function. External event input pin. Counter reset input pin. Counter start trigger input pin. External event input pin. Output compare output/ input capture input/ PWM output pin Transmit data output pin
TMCIV TMRIV TRGV Timer W FTCI FTIOA to FTIOD Serial communication interface (SCI) TXD, TXD_2, TXD_3* RXD, RXD_2, RXD_3* SCK3, SCK3_2, SCK3_3* A/D converter I/O ports ADTRG
29 28 54 36 37 to 40 46, 56, 27
23 22 40 26 27 to 30 36, 42, 21
Input Input Input Input I/O Output
45, 57, 26
35, 43, 20
Input
Receive data input pin
44, 58, 25
34, 44, 19
I/O
Clock I/O pin
AN3 to AN0 59 to 62 22
45 to 48 16 45 to 48 40 to 37, 19 to 17 36 to 34 21, 20, 16 to 11 24 to 22, 41 to 44 30 to 26 31, 32, 33
Input Input Input I/O I/O I/O
Analog input pin A/D converter trigger input pin. 4-bit input port. 7-bit I/O port. 3-bit I/O port. 8-bit I/O port
PB3 to PB0 59 to 62 P17 to P14, 54 to 51, P12 to P10 25 to 23 P22 to P20 P57 to P50 46 to 44 27, 26, 22 to 19, 14, 13 30 to 28, 55 to 58 40 to 36 41, 42, 43
P76 to P70 P84 to P80 E10T E10T _0, E10T _1, E10T _2 *
I/O I/O
7-bit I/O port 5-bit I/O port. Interface pin for the E10T, E8, or E7 emulator
Note:
The SCK3_3, RXD_3, and TXD_3 pins are not multiplexed in the H8/36014.
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Section 1 Overview
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Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. * Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added. * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-two basic instructions 8/16/32-bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 64-kbyte address space * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract : 2 state 8 x 8-bit register-register multiply : 14 states 16 / 8-bit register-register divide : 14 states 16 x 16-bit register-register multiply : 22 states 32 / 16-bit register-register divide : 22 states * Power-down state Transition to power-down state by SLEEP instruction
CPU30H2E_000120030300
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Section 2 CPU
2.1
Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory maps.
H8/36024F H8/36014F (Flash memory version) H'0000 H'0045 H'0046 Interrupt vector
H'0000 H'0045 H'0046
H8/36022F H8/36012F (Flash memory version)
H8/36024 H8/36014 (Masked ROM version)
H'0000 H'0045 H'0046
H8/36023 H8/36013 (Masked ROM version) H'0000 H'0045 H'0046 Interrupt vector
Interrupt vector
Interrupt vector
On-chip ROM (16 kbytes)
On-chip ROM (24 kbytes)
On-chip ROM (32 kbytes)
H'3FFF
On-chip ROM (32 kbytes)
H'5FFF
Not used H'7FFF
H'7FFF
Not used Not used
Not used H'F600 H'F74F H'F780 (1-kbyte work area for flash memory programming) H'FB7F H'FB80 On-chip RAM (2 kbytes)
H'FB7F H'FB80 H'F600 H'F74F H'F780
H'F600 H'F74F
Internal I/O register
Internal I/O register
Internal I/O register
H'F600 H'F74F
Internal I/O register
(1-kbyte work area for flash memory programming) On-chip RAM (2 kbytes)
Not used
Not used
H'FB80
H'FB80
(1-kbyte user area) H'FF7F H'FF80 Internal I/O register H'FFFF
H'FFFF H'FF7F H'FF80
(1-kbyte user area)
H'FF7F H'FF80
On-chip RAM (1 kbyte)
H'FF7F H'FF80
On-chip RAM (1 kbyte)
Internal I/O register
H'FFFF
Internal I/O register
H'FFFF
Internal I/O register
Figure 2.1 Memory Map (1)
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Section 2 CPU
H8/36022 H8/36012 (Masked ROM version) H'0000 H'0045 H'0046 Interrupt vector H'0000 H'0045 H'0046
H8/36011 (Masked ROM version) Interrupt vector H'0000 H'0045 H'0046
H8/36010 (Masked ROM version) Interrupt vector On-chip ROM (8 kbytes) H'1FFF
On-chip ROM (16 kbytes)
On-chip ROM (12 kbytes) H'2FFF
H'3FFF
Not used Not used
Not used
H'F600 H'F74F
Internal I/O register
H'F600 H'F74F
Internal I/O register
H'F600 H'F74F
Internal I/O register
Not used
Not used
Not used
H'FD80 H'FF7F H'FF80 H'FFFF
H'FD80 On-chip RAM (512 bytes) Internal I/O register H'FFFF H'FF7F H'FF80 On-chip RAM (512 bytes) Internal I/O register
H'FD80 H'FF7F H'FF80 H'FFFF On-chip RAM (512 bytes) Internal I/O register
Figure 2.1 Memory Map (2)
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2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR).
General Registers (ERn)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR)
23 PC 0
76543210
CCR I UI H U N Z V C
Legend
SP PC CCR I UI :Stack pointer :Program counter :Condition-code register :Interrupt mask bit :User bit H U N Z V C :Half-carry flag :User bit :Negative flag :Zero flag :Overflow flag :Carry flag
Figure 2.2 CPU Registers
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2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. The usage of each register can be selected independently.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H)
Figure 2.3 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the stack.
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Free area SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see Appendix A.1, Instruction List.
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Bit 7
Bit Name I
Initial Value 1
R/W R/W
Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
6
UI
Undefined R/W
User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag Stores the value of the most significant bit of data as a sign bit.
2
Z
Undefined R/W
Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
1
V
Undefined R/W
Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
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2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type
1-bit data
General Register
RnH
Data Format
7 0 Don't care
7
0
76 54 32 10
1-bit data
RnL
Don't care
76 54 32 10
7
4-bit BCD data RnH Upper
43
Lower
0
Don't care
7
4-bit BCD data RnL
43
Upper Lower
0
Don't care
7
Byte data RnH
0
Don't care
MSB
LSB
7
Byte data RnL
0 LSB
Don't care
MSB
Figure 2.5 General Register Data Formats (1)
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Data Type Word data
General Register Rn
Data Format
15
0
Word data
En
15 0
MSB
LSB
MSB
LSB
16 15
0
Longword data
ERn
31
MSB
LSB
Legend
ERn En Rn RnH RnL LSB : General register ER : General register E : General register R : General register RH : General register RL : Least significant bit
MSB : Most significant bit
Figure 2.5 General Register Data Formats (2)
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2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 (SP) is used as an address register to access the stack, the operand size should be word or longword.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Format
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M+1
MSB LSB
Longword data
Address 2N Address 2N+1 Address 2N+2 Address 2N+3
MSB
LSB
Figure 2.6 Memory Data Formats
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Section 2 CPU
2.4
2.4.1
Instruction Set
Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1
Symbol Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x /
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement)
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Symbol :3/:8/:16/:24 Note: *
Description 3-, 8-, 16-, or 24-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address registers (ER0 to ER7).
Table 2.2
Instruction MOV
Data Transfer Instructions
Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) Rd, Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
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Table 2.3
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU
B
B/W/L
L B
B/W
MULXS
B/W
DIVXU
B/W
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
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Table 2.3
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
Table 2.4
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement of general register contents.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
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Note:
* Refers to the operand size. B: Byte W: Word L: Longword
Table 2.5
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note:
Shift Instructions
Size* B/W/L B/W/L B/W/L B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry flag.
* Refers to the operand size. B: Byte W: Word L: Longword
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Table 2.6
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
Note:
* Refers to the operand size. B: Byte
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Table 2.6
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B Function C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
Note:
* Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction Bcc*
Branch Instructions
Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1
JMP BSR JSR RTS Note: *
-- -- -- --
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
Bcc is the general name for conditional branch instructions.
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Table 2.8
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. CCR (EAd), EXR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically XORs the CCR with immediate data. PC + 2 PC Only increments the program counter.
STC
B/W
ANDC ORC XORC NOP Note:
B B B --
* Refers to the operand size. B: Byte W: Word
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Section 2 CPU
Table 2.9
Instruction EEPMOV.B
Block Data Transfer Instructions
Size -- Function if R4L 0 then Repeat @ER5+ @ER6+, R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+, R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
--
2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.7 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). * Condition Field Specifies the branching condition of Bcc instructions.
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(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm
(4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8
Figure 2.7 Instruction Formats
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2.5
Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to Appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.10 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:24,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
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(1)
Register Direct--Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect--@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn
* Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. (5) Absolute Address--@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space.
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The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11, because the upper 8 bits are ignored. Table 2.11 Absolute Address Access Ranges
Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Access Range H'FF00 to H'FFFF H'0000 to H'FFFF H'0000 to H'FFFF
(6)
Immediate--#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative--@(d:8, PC) or @(d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect--@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF). Note that the first part of the address range is also the exception vector area.
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Specified by @aa:8
Dummy Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31
General register contents
Register indirect(@ERn)
0
23
0
op 3
r
Register indirect with displacement @(d:16,ERn) or @(d:24,ERn)
31
General register contents
0 23 0
op
r
disp 31
Sign extension
0 disp
4
Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+
31
General register contents
0
23
0
op
r 31
1, 2, or 4
*Register indirect with pre-decrement @-ERn
0
General register contents
23
0
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
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Section 2 CPU
Table 2.12 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8 op abs
23 H'FFFF
87
0
@aa:16 op abs
23
16 15
0
Sign extension
@aa:24 op abs 23 0
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:8,PC) @(d:16,PC)
23
PC contents
0
op
disp
23
Sign extension
0 disp 23 0
8
Memory indirect @@aa:8
23 op abs H'0000 15
87 abs
0
0
Memory contents
23
16 15 H'00
0
Legend r, rm,rn : op : disp : IMM : abs :
Register field Operation field Displacement Immediate data Absolute address
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Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock () or a subclock (SUB). The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle
T1 state
o or o SUB
T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal
Internal data bus (write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
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Section 2 CPU
2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 17.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module.
Bus cycle
T1 state
o or o SUB
T2 state
T3 state
Internal address bus Internal read signal Internal data bus (read access) Internal write signal
Internal data bus (write access)
Address
Read data
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, and standby mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes. For details on exception processing, refer to section 3, Exception Handling.
CPU state
Reset state The CPU is initialized Program execution state
Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock
The CPU executes successive program instructions at reduced speed, synchronized by the subclock Program halt state A state in which some or all of the chip functions are stopped to conserve power Sleep mode Power-down modes Standby mode
Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operation States
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Section 2 CPU
Reset cleared Reset state
Reset occurs
Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Interrupt source
Exceptionhandling complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.12 State Transitions
2.8
2.8.1
Usage Notes
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). 2.8.3 Bit Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated.
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Section 2 CPU
(1)
Bit manipulation for two registers assigned to the same address
Example: Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the group of this LSI.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register.
Read Count clock Timer counter
Reload
Write Timer load register
Internal bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address
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Section 2 CPU
Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below. * Prior to executing BSET
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BSET instruction executed BSET #0, @PDR5 The BSET instruction is executed for port 5.
* After executing BSET
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 0 P56 Input High level 0 1 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output High level 1 1
* Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET.
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Section 2 CPU
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. * Prior to executing BSET MOV.B MOV.B MOV.B #80, R0L, R0L,
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1
R0L @RAM0 @PDR5
P56 Input High level 0 0 0
The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output Low level 1 0 0
* BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0).
* After executing BSET MOV.B MOV.B @RAM0, R0L R0L, @PDR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0
The work area (RAM0) value is written to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output High level 1 1 1
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Section 2 CPU
(2)
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. * Prior to executing BCLR
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BCLR instruction executed BCLR #0, @PCR5 The BCLR instruction is executed for PCR5.
* After executing BCLR
P57 Input/output Pin state PCR5 PDR5 Output Low level 1 1 P56 Output High level 1 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Input High level 0 0
* Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F. 2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PCR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PCR5.
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Section 2 CPU
* Prior to executing BCLR MOV.B MOV.B MOV.B #3F, R0L, R0L,
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0
R0L @RAM0 @PCR5
P56 Input High level 0 0 0
The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output Low level 1 0 1
* BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0).
* After executing BCLR MOV.B MOV.B @RAM0, R0L R0L, @PCR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0
The work area (RAM0) value is written to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output High level 0 0 0
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Section 2 CPU
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Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. * Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. * Trap Instruction Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction code. Exception handling can be executed at all times in the program execution state. * Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued.
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.1 Exception Sources and Vector Address
Exception Sources Reset Reserved for system use NMI Trap instruction (#0) (#1) (#2) (#3) Address break Break conditions satisfied Vector Number Vector Address 0 1 to 6 7 8 9 10 11 12 H'0000 to H'0001 H'0002 to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 Low Priority High
Relative Module RES pin Watchdog timer External interrupt pin CPU
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Section 3 Exception Handling
Relative Module CPU External interrupt pin
Exception Sources Direct transition by executing the SLEEP instruction IRQ0 Low-voltage detection interrupt*1 IRQ3 WKP
Vector Number Vector Address 13 14
Priority
H'001A to H'001B High H'001C to H'001D
17 18 20 21
H'0022 to H'0023 H'0024 to H'0025 H'0028 to H'0029 H'002A to H'002B
Timer W
Reserved for system use Timer W input capture A /compare match A Timer W input capture B /compare match B Timer W input capture C /compare match C Timer W input capture D /compare match D Timer W overflow Timer V compare match A Timer V compare match B Timer V overflow SCI3 receive data full SCI3 transmit data empty SCI3 transmit end SCI3 receive error A/D conversion end SCI3_2 receive data full SCI3_2 transmit data empty SCI3_2 transmit end SCI3_2 receive error SCI3_3 receive data full SCI3_3 transmit data empty SCI3_3 transmit end SCI3_3 receive error
Timer V
22
H'002C to H'002D
SCI3
23
H'002E to H'002F
A/D converter SCI3_2
25 32
H'0032 to H'0033 H'0040 to H'0041
SCI3_3*2
34
H'0044 to H'0045
Low
Notes: 1. A low-voltage detection interrupt is enabled only in the product with an on-chip poweron reset and low-voltage detection circuit. 2. The SCI3_3 function is incorporated in the H8/36024.
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Section 3 Exception Handling
3.2
Register Descriptions
Interrupts are controlled by the following registers. * * * * * Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt flag register 1 (IRR1) Wakeup interrupt flag register (IWPR) Interrupt Edge Select Register 1 (IEGR1)
3.2.1
IEGR1 selects the direction of an edge that generates interrupt requests of pins and IRQ3 and IRQ0.
Bit 7 6 to 4 3 Bit Name IEG3 Initial Value 0 All 1 0 R/W - R/W Description Reserved This bit is always read as 0. Reserved These bits are always read as 1. IRQ3 Edge Select 0: Falling edge of IRQ3 pin input is detected 1: Rising edge of IRQ3 pin input is detected 2, 1 0 IEG0 All 0 0 R/W Reserved These bits are always read as 0. IRQ0 Edge Select 0: Falling edge of IRQ0 pin input is detected 1: Rising edge of IRQ0 pin input is detected
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Section 3 Exception Handling
3.2.2
Interrupt Edge Select Register 2 (IEGR2)
IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0.
Bit 7, 6 5 Bit Name WPEG5 Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. WKP5 Edge Select 0: Falling edge of WKP5 (ADTRG) pin input is detected 1: Rising edge of WKP5 (ADTRG) pin input is detected 4 WPEG4 0 R/W WKP4 Edge Select 0: Falling edge of WKP4 pin input is detected 1: Rising edge of WKP4 pin input is detected 3 WPEG3 0 R/W WKP3 Edge Select 0: Falling edge of WKP3 pin input is detected 1: Rising edge of WKP3 pin input is detected 2 WPEG2 0 R/W WKP2 Edge Select 0: Falling edge of WKP2 pin input is detected 1: Rising edge of WKP2 pin input is detected 1 WPEG1 0 R/W WKP1Edge Select 0: Falling edge of WKP1 pin input is detected 1: Rising edge of WKP1 pin input is detected 0 WPEG0 0 R/W WKP0 Edge Select 0: Falling edge of WKP0 pin input is detected 1: Rising edge of WKP0 pin input is detected
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Section 3 Exception Handling
3.2.3
Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts, and external pin interrupts.
Bit 7 Bit Name IENDT Initial Value 0 R/W R/W Description Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 5 IENWP 0 0 R/W Reserved This bit is always read as 0. Wakeup Interrupt Enable This bit is an enable bit, which is common to the pins WKP5 to WKP0. When the bit is set to 1, interrupt requests are enabled. 4 3 IEN3 1 0 R/W Reserved This bit is always read as 1. IRQ3 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ3 pin are enabled. 2, 1 0 IEN0 All 0 0 R/W Reserved These bits are always read as 0. IRQ0 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ0 pin are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.
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Section 3 Exception Handling
3.2.4
Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests.
Bit 7 Bit Name IRRDT Initial Value 0 R/W R/W Description Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1. [Clearing condition] When IRRDT is cleared by writing 0 6 5, 4 3 IRRI3 0 All 1 0 R/W Reserved This bit is always read as 0. Reserved These bits are always read as 1. IRQ3 Interrupt Request Flag [Setting condition] When IRQ3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI3 is cleared by writing 0 2, 1 0 IRRl0 All 0 0 R/W Reserved These bits are always read as 0. IRQ0 Interrupt Request Flag [Setting condition] When IRQ0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI0 is cleared by writing 0
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Section 3 Exception Handling
3.2.5
Wakeup Interrupt Flag Register (IWPR)
Initial Value All 1 0
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Bit 7, 6 5 Bit Name IWPF5 R/W R/W Description Reserved These bits are always read as 1. WKP5 Interrupt Request Flag [Setting condition] When WKP5 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF5 is cleared by writing 0. 4 IWPF4 0 R/W WKP4 Interrupt Request Flag [Setting condition] When WKP4 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF4 is cleared by writing 0. 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0. 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0. 1 IWPF1 0 R/W WKP1 Interrupt Request Flag [Setting condition] When WKP1 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF1 is cleared by writing 0.
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Section 3 Exception Handling
Bit 0
Bit Name IWPF0
Initial Value 0
R/W R/W
Description WKP0 Interrupt Request Flag [Setting condition] When WKP0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF0 is cleared by writing 0.
3.3
Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling. The reset exception handling sequence is shown in figure 3.1. The reset exception handling sequence is as follows. However, for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer to section 15, Power-On Reset and Low-Voltage Detection Circuits (Optional). 1. Set the I bit in the condition code register (CCR) to 1. 2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the data in that address is sent to the program counter (PC) as the start address, and program execution starts from that address.
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Section 3 Exception Handling
3.4
3.4.1
Interrupt Exception Handling
External Interrupts
There are external interrupts, NMI, IRQ3, IRQ0, and WKP. (1) NMI
NMI interrupt is requested by input falling edge to pin NMI. NMI is the highest interrupt, and can always be accepted without depending on the I bit value in CCR. (2) IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1. When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. When IRQ3 to IRQ0 interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1. (3) WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2. When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bit IENWP in IENR1.
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Section 3 Exception Handling
Reset cleared
Initial program instruction prefetch Vector fetch Internal processing
RES
o
Internal address bus Internal read signal Internal write signal Internal data bus (16 bits)
(1)
(2)
(2)
(3)
(1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction
Figure 3.1 Reset Sequence 3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1. When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable bit.
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Section 3 Exception Handling
3.4.3
Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. The CPU accepts the NMI or address break without depending on the I bit value. Other interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the interrupt request is held pending. 4. If the CPU accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be restored and returned to the values prior to the start of interrupt exception handling. 6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and transfers the address to PC as a start address of the interrupt handling-routine. Then a program starts executing from the address indicated in PC. Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
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Section 3 Exception Handling
SP - 4
SP (R7)
CCR CCR*3 PCH PCL Even address
SP - 3 SP - 2 SP - 1 SP (R7)
Stack area
SP + 1
SP + 2 SP + 3 SP + 4
Prior to start of interrupt exception handling
PC and CCR saved to stack
After completion of interrupt exception handling
Legend: PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word length, starting from an even-numbered address. 3. Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status after Exception Handling 3.4.4 Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2
Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Note: * Not including EEPMOV instruction.
Interrupt Wait States
States 1 to 23 4 2 4 4 Total 15 to 37
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Interrupt is accepted
Interrupt level decision and wait for end of instruction Instruction prefetch Internal processing
Stack access
Vector fetch
Prefetch instruction of Internal interrupt-handling routine processing
Interrupt request signal
o
Internal address bus
(1)
(3)
(5) (6)
(8)
(9)
Internal read signal
Internal write signal (2)
(4)
(1)
(7)
Figure 3.3 Interrupt Sequence
(9)
Internal data bus (16 bits)
(10)
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(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine
Section 3 Exception Handling
REJ09B0025-0400
Section 3 Exception Handling
3.5
3.5.1
Usage Notes
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.W #xx: 16, SP). 3.5.2 Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. 3.5.3 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3, IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1. Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0.
Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.)
CCR I bit 1
Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0
CCR I bit 0
Interrupt mask cleared
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
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Section 4 Address Break
Section 4 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. With the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. Figure 4.1 shows a block diagram of the address break.
Internal address bus
Comparator
BARH Interrupt generation control circuit BDRH
BARL ABRKCR ABRKSR BDRL Internal data bus Interrupt
Comparator
Legend: BARH, BARL: BDRH, BDRL: ABRKCR: ABRKSR:
Break address register Break data register Address break control register Address break status register
Figure 4.1 Block Diagram of Address Break
4.1
Register Descriptions
Address break has the following registers. * Address break control register (ABRKCR) * Address break status register (ABRKSR) * Break address register (BARH, BARL)
ABK0001A_000020020200
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Section 4 Address Break
* Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR)
ABRKCR sets address break conditions.
Bit 7 Bit Name RTINTE Initial Value 1 R/W R/W Description RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 5 CSEL1 CSEL0 0 0 R/W R/W Condition Select 1 and 0 These bits set address break conditions. 00: Instruction execution cycle 01: CPU data read cycle 10: CPU data write cycle 11: CPU data read/write cycle 4 3 2 ACMP2 ACMP1 ACMP0 0 0 0 R/W R/W R/W Address Compare Condition Select 2 to 0 These bits comparison condition between the address set in BAR and the internal address bus. 000: Compares 16-bit addresses 001: Compares upper 12-bit addresses 010: Compares upper 8-bit addresses 011: Compares upper 4-bit addresses 1XX: Reserved (setting prohibited) 1 0 DCMP1 DCMP0 0 0 R/W R/W Data Compare Condition Select 1 and 0 These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus Legend: X: Don't care.
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Section 4 Address Break
When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 17.1, Register Addresses (Address Order). Table 4.1 Access and Data Bus Used
Word Access Even Address Odd Address ROM space RAM space Upper 8 bits Upper 8 bits Lower 8 bits Lower 8 bits Upper 8 bits Lower 8 bits Byte Access Even Address Odd Address Upper 8 bits Upper 8 bits Upper 8 bits -- Upper 8 bits Upper 8 bits Upper 8 bits --
I/O register with 8-bit data bus Upper 8 bits width I/O register with 16-bit data bus width Upper 8 bits
4.1.2
Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit 7 Bit Name ABIF Initial Value 0 R/W R/W Description Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled. 5 to 0 -- All 1 -- Reserved These bits are always read as 1.
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Section 4 Address Break
4.1.3
Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 4.1.4 Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH for byte access. For word access, the data bus used depends on the address. See section 4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is undefined.
4.2
Operation
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked because of the I bit in CCR of the CPU.
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Section 4 Address Break
Figures 4.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting * ABRKCR = H'80 * BAR = H'025A
Program 0258 * 025A 025C 0260 0262 :
NOP NOP MOV.W @H'025A,R0 NOP NOP :
Underline indicates the address to be stacked.
NOP MOV MOV NOP instruc- instruc- instruc- instruction tion 1 tion 2 Internal tion prefetch prefetch prefetch prefetch processing
Stack save
Address bus Interrupt request
Interrupt acceptance
0258
025A
025C
025E
SP-2
SP-4
Figure 4.2 Address Break Interrupt Operation Example (1)
When the address break is specified in the data read cycle
Register setting * ABRKCR = H'A0 * BAR = H'025A
Program 0258 025A * 025C 0260 0262 :
NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked. :
MOV NOP MOV NOP Next MOV instruc- instruc- instruc- instruc- instruc- instrution 2 tion tion tion ction Internal Stack tion 1 prefetch prefetch prefetch execution prefetch prefetch processing save
Address bus Interrupt request
Interrupt acceptance
025C
025E
0260
025A
0262
0264
SP-2
Figure 4.2 Address Break Interrupt Operation Example (2)
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Section 4 Address Break
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Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. Figure 5.1 shows a block diagram of the clock pulse generators.
OSC1 OSC2
System clock oscillator
OSC (fOSC)
Duty correction circuit
OSC (fOSC)
System clock divider
OSC OSC/8 OSC/16 OSC/32 OSC/64
/2 to /8192
System clock pulse generator
Prescaler S (13 bits)
Figure 5.1 Block Diagram of Clock Pulse Generators The basic clock signals that drive the CPU and on-chip peripheral modules are system clocks (). The system clock is divided into /8192 to /2 by prescaler S and they are supplied to respective peripheral modules.
5.1
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator.
OSC 2
LPM OSC 1 LPM: Low-power mode (standby mode, subsleep mode)
Figure 5.2 Block Diagram of System Clock Generator
CPG0200A_000020020200
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Section 5 Clock Pulse Generators
5.1.1
Connecting Crystal Resonator
Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 5.1 should be used.
C1
OSC 1 OSC 2
C2
C1 = C 2 = 12 pF 20%
Figure 5.3 Typical Connection to Crystal Resonator
LS
RS
CS
OSC 1
C0
OSC 2
Figure 5.4 Equivalent Circuit of Crystal Resonator Table 5.1 Crystal Resonator Parameters
2 500 7 pF 4 120 7 pF 8 80 7 pF 10 60 7 pF 16 50 7 pF 20 40 7 pF
Frequency (MHz) RS (max) C0 (max)
5.1.2
Connecting Ceramic Resonator
Figure 5.5 shows a typical method of connecting a ceramic resonator.
C1 OSC1 C2 OSC2 C1 = 30 pF 10% C2 = 30 pF 10%
Figure 5.5 Typical Connection to Ceramic Resonator
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Section 5 Clock Pulse Generators
5.1.3
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.6 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
External clock input
OSC 2
Open
Figure 5.6 Example of External Clock Input
5.2
5.2.1
Prescalers
Prescaler S
Prescaler S is a 13-bit counter using the system clock () as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral function. In active mode and sleep mode, the clock input to prescaler S is determined by the division factor designated by MA2 to MA0 in SYSCR2.
5.3
5.3.1
Usage Notes
Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator element manufacturer. Design the circuit so that the resonator element never receives voltages exceeding its maximum rating.
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Section 5 Clock Pulse Generators
5.3.2
Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.7).
Avoid
Signal A
Signal B
C1 OSC1 C2 OSC2
Figure 5.7 Example of Incorrect Board Design
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Section 6 Power-Down Modes
Section 6 Power-Down Modes
This LSI has five modes of operation after a reset. These include a normal active mode and three power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. * Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc, osc/8, osc/16, osc/32, and osc/64. * Sleep mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Standby mode The CPU and all on-chip peripheral modules halt. * Subsleep mode The CPU and all on-chip peripheral modules halt. I/O ports keep the same states as before the transition. * Module standby mode Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units.
6.1
Register Descriptions
The registers related to power-down modes are listed below. * * * * System control register 1 (SYSCR1) System control register 2 (SYSCR2) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2)
LPW3003A_000020020200
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Section 6 Power-Down Modes
6.1.1
System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction. 0: a transition is made to sleep mode 1: a transition is made to standby mode. For details, see table 6.2. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, to active mode or sleep mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. The relationship between the specified value and the number of wait states is shown in table 6.1. When an external clock is to be used, the minimum value (STS2 = STS1 = STS0 =1) is recommended. Reserved These bits are always read as 0.
3 to 0
All 0
Table 6.1
Operating Frequency and Waiting Time
Operating Frequency 20 MHz 16 MHz 0.4 0.8 1.6 3.3 6.6 0.05 0.00 0.00 0.5 1.0 2.0 4.1 8.2 0.06 0.00 0.00 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0.8 1.6 3.3 6.6 13.1 0.10 0.01 0.00 1.0 2.0 4.1 8.2 16.4 0.13 0.02 0.00 2.0 4.1 8.2 16.4 32.8 0.26 0.03 0.00 4.1 8.2 16.4 32.8 65.5 0.51 0.06 0.01 8.1 16.4 32.8 65.5 16.4 32.8 65.5 131.1
Bit Name STS2 STS1 STS0 Waiting Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 1,024 states 128 states 16 states
131.1 262.1 1.02 0.13 0.02 2.05 0.26 0.03
Note: Time unit is ms.
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Section 6 Power-Down Modes
6.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit 7 Bit Name SMSEL Initial Value 0 R/W R/W Description Sleep Mode Selection This bit selects the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2. 6 5 DTON 0 0 R/W Reserved This bit is always read as 0. Direct Transfer on Flag This bit selects the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2. 4 3 2 MA2 MA1 MA0 0 0 0 R/W R/W R/W Active Mode Clock Select 2 to 0 These bits select the operating clock frequency in active and sleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 0XX: OSC 100: OSC/8 101: OSC/16 110: OSC/32 111: OSC/64 1, 0 All 0 Reserved These bits are always read as 0. Legend: X : Don't care.
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Section 6 Power-Down Modes
6.1.3
Module Standby Control Register 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Bit 7, 6 5 4 Bit Name MSTS3 MSTAD Initial Value All 0 0 0 R/W R/W R/W Description Reserved These bits are always read as 0. SCI3 Module Standby SCI3 enters standby mode when this bit is set to 1. A/D Converter Module Standby A/D converter enters standby mode when this bit is set to 1. 3 MSTWD 0 R/W Watchdog Timer Module Standby Watchdog timer enters standby mode when this bit is set to 1.When the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit. 2 1 0 MSTTW MSTTV 0 0 0 R/W R/W Timer W Module Standby Timer W enters standby mode when this bit is set to 1. Timer V Module Standby Timer V enters standby mode when this bit is set to 1. Reserved This bit is always read as 0.
6.1.4
Module Standby Control Register 2 (MSTCR2)
MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units.
Bit 7 6 to 0 Bit Name MSTS3_2 Initial Value 0 All 0 R/W R/W Description SCI3_2 Module Standby SCI3_2 enters standby mode when this bit is set to1. Reserved These bits are always read as 0.
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Section 6 Power-Down Modes
6.2
Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition from active mode to active mode changes the operating frequency. RES input enables transitions from a mode to the reset state. Table 6.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 6.3 shows the internal states of the LSI in each mode.
Reset state Program halt state SLEEP instruction Standby mode Interrupt Active mode Interrupt SLEEP instruction Program execution state Direct transition interrupt SLEEP instruction Sleep mode Program halt state
Interrupt
Subsleep mode
Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. Details on the mode transition conditions are given in table 6.2.
Figure 6.1 Mode Transition Diagram
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Section 6 Power-Down Modes
Table 6.2
DTON 0
Transition Mode after SLEEP Instruction Execution and Interrupt Handling
SSBY 0 0 1 SMSEL 0 1 X 0* Transition Mode after SLEEP Transition Mode due to Instruction Execution Interrupt Sleep mode Subsleep mode Standby mode Active mode (direct transition) Active mode Active mode Active mode --
1 Legend: *
X
X: Don't care. When a state transition is performed while SMSEL is 1, timer V, SCI3, SCI3_2, SCI3_3 (only for the H8/36024) and the A/D converter are reset, and all registers are set to their initial values. To use these functions after entering active mode, reset the registers.
Table 6.3
Function
Internal State in Each Operating Mode
Active Mode Functioning Functioning Functioning Functioning Functioning Sleep Mode Functioning Halted Retained Retained Retained Subsleep Mode Halted Halted Retained Retained Retained Standby Mode Halted Halted Retained Retained Register contents are retained, but output is the high-impedance state. Functioning Functioning Reset Retained (if internal clock is selected as a count clock, the counter is incremented by a subclock) Retained (functioning if the internal oscillator is selected as a count clock) Reset Reset
System clock oscillator CPU operations RAM IO ports Instructions Registers
External interrupts
IRQ3, IRQ0 WKP5 to WKP0 Timer V Timer W
Functioning Functioning Functioning Functioning
Functioning Functioning Functioning Functioning
Functioning Functioning Reset Retained
Peripheral functions
Watchdog timer SCI3 A/D converter
Functioning
Functioning
Retained
Functioning Functioning
Functioning Functioning
Reset Reset
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Section 6 Power-Down Modes
6.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register. a transition is made to subactive mode when the bit is 1. When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 6.2.2 Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2-STS0 in SYSCR1 has elapsed, and interrupt exception handling starts. Standby mode is not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. 6.2.3 Subsleep Mode
In subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip peripheral modules is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, the system clock oscillator starts to oscillate. Subsleep mode is cleared and an interrupt exception handling starts when the time set in bits STS2 to STS0 in SYSCR1 elapses. Subsleep mode is not cleared if the I bit of CCR is 1 or the interrupt is disabled in the interrupt enable bit.
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Section 6 Power-Down Modes
6.3
Operating Frequency in Active Mode
Operation in active mode is clocked at the frequency designated by the MA2 to MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution.
6.4
Direct Transition
The CPU can execute programs in active mode. The operating frequency can be changed by making a transition directly from active mode to active mode. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active mode. After the mode transition, direct transition interrupt exception handling starts. If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made instead to sleep mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep mode will be entered, and the resulting mode cannot be cleared by means of an interrupt.
6.5
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the clock supply to modules stops to enter the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds to each module in MSTCR1 and MSTCR2 to 1 and cancels the mode by clearing the bit to 0.
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Section 7 ROM
Section 7 ROM
The features of the 32-kbyte (4 kbytes of them are the control program area for E7 or E8) flash memory built into the HD64F36024 and HD64F36014 are summarized below. * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte x 4 blocks and 28 kbytes x 1 block. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed up to 1,000 times. * On-board programming On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing.
ROM3321A_000120030300
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Section 7 ROM
7.1
Block Configuration
Figure 7.1 shows the block configuration of 32-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 1 kbyte x 4 blocks and 28 kbytes x 1 block. Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
H'0000
Erase unit 1kbyte
H'0001 H'0081
H'0002 H'0082
Programming unit: 128 bytes
H'007F H'00FF
H'0080
H'0380 H'0400
Erase unit 1kbyte
H'0381 H'0401 H'0481
H'0382 H'0402 H'0481
Programming unit: 128 bytes
H'03FF H'047F H'04FF
H'0480
H'0780 H'0800
Erase unit 1kbyte
H'0781 H'0801 H'0881
H'0782 H'0802 H'0882
Programming unit: 128 bytes
H'07FF H'087F H'08FF
H'0880
H'0B80 H'0C00
Erase unit 1kbyte
H'0B81 H'0C01 H'0C81
H'0B82 H'0C02 H'0C82
Programming unit: 128 bytes
H'0BFF H'0C7F H'0CFF
H'0C80
H'0F80 H'1000
Erase unit 28 kbytes
H'0F81 H'1001 H'1081
H'0F82 H'1002 H'1082
Programming unit: 128 bytes
H'0FFF H'107F H'10FF
H'1080
H'7F80
H'7F81
H'7F82
H'7FFF
Figure 7.1 Flash Memory Block Configuration
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Section 7 ROM
7.2
Register Descriptions
The flash memory has the following registers. * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory enable register (FENR) Flash Memory Control Register 1 (FLMCR1)
7.2.1
FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing.
Bit 7 6 Bit Name -- SWE Initial Value 0 0 R/W -- R/W Description Reserved This bit is always read as 0. Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit to 1 in FLMCR1. 4 PSU 0 R/W Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1. 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled.
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Section 7 ROM
Bit 2
Bit Name PV
Initial Value 0
R/W R/W
Description Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled.
1
E
0
R/W
Erase When this bit is set to 1, and while the SWE = 1 and ESU = 1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled.
0
P
0
R/W
Program When this bit is set to 1, and while the SWE = 1 and PSU = 1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled.
7.2.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See 7.5.3, Error Protection, for details. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
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Section 7 ROM
7.2.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0.
Bit 7 to 5 4 3 2 1 0 Bit Name -- EB4 EB3 EB2 EB1 EB0 Initial Value All 0 0 0 0 0 0 R/W -- R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF will be erased. When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will be erased. When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will be erased. When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will be erased. When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will be erased.
7.2.4
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, and EBR1.
Bit 7 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
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Section 7 ROM
7.3
On-Board Programming Modes
There is a mode for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 7.1
TEST 0 0
Setting Programming Modes
NMI 1 0 E10T_0 X 1 PB0 X X PB1 X X PB2 X X LSI State after Reset End User Mode Boot Mode
Legend: X: Don't care.
7.3.1
Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period.
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Section 7 ROM
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 7.3. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to H'FEEF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR3 to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD pin is high (PCR22 = 1, P22 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the NMI pin. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the TEST pin and NMI pin input levels in boot mode.
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Section 7 ROM
Table 7.2
Item
Boot Mode Operation
Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program at reset-start.
Boot mode initiation
Boot program initiation
Bit rate adjustment
Continuously transmits data H'00 at specified bit rate.
H'00, H'00 . . . H'00
Transmits data H'55 when data H'00 is received error-free.
H'00
* Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end indication. H'55 reception.
H'55
Flash memory erase
Boot program erase error
H'FF
H'AA reception
H'AA
Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.)
Transfer of number of bytes of programming control program
Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte)
Upper bytes, lower bytes Echoback
Echobacks the 2-byte data received to host.
Transmits 1-byte of programming control program (repeated for N times)
H'XX Echoback
Echobacks received data to host and also transfers it to RAM. (repeated for N times)
H'AA reception
H'AA
Transmits data H'AA to host.
Branches to programming control program transferred to on-chip RAM and starts execution.
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Section 7 ROM
Table 7.3
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible
System Clock Frequency Range of LSI 16 to 20 MHz 8 to 16 MHz 4 to 16 MHz 2 to 16 MHz
Host Bit Rate 19,200 bps 9,600 bps 4,800 bps 2,400 bps
7.3.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing.
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control program to RAM
Branch to flash memory application program
Branch to user program/erase control program in RAM
Execute user program/erase control program (flash memory rewrite)
Branch to flash memory application program
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
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Section 7 ROM
7.4
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2, Erase/Erase-Verify, respectively. 7.4.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words or in longwords from the address to which a dummy write was performed.
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Section 7 ROM
8.
The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Write pulse application subroutine
Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait time=programming time) Clear P bit in FLMCR1 Wait 5 s Clear PSU bit in FLMCR1 Wait 5 s
Disable WDT
START Set SWE bit in FLMCR1 Wait 1 s
*
Store 128-byte program data in program data area and reprogram data area
n= 1 m= 0
Write 128-byte data in RAM reprogram data area consecutively to flash memory
Apply Write pulse Set PV bit in FLMCR1 Wait 4 s Set block start address as verify address
nn+1 H'FF dummy write to verify address
End Sub
Wait 2 s
Read verify data Increment address Verify data = write data?
*
No m=1 No
Yes n6?
Yes Additional-programming data computation
Reprogram data computation
No
128-byte data verification completed?
Yes Clear PV bit in FLMCR1 Wait 2 s n 6? Yes Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse No Yes No
m= 0 ? Yes Clear SWE bit in FLMCR1 Wait 100 s
End of programming
n 1000 ?
No Clear SWE bit in FLMCR1 Wait 100 s
Programming failure
Note: *The RTS instruction must not be used during the following 1. and 2. periods. 1. A period between 128-byte data programming to flash memory and the P bit clearing 2. A period between dummy writing of H'FF to a verify address and verify data reading
Figure 7.3 Program/Program-Verify Flowchart
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Section 7 ROM
Table 7.4
Reprogram Data Computation Table
Verify Data 0 1 0 1 Reprogram Data 1 0 1 1 Comments Programming completed Reprogram bit -- Remains in erased state
Program Data 0 0 1 1
Table 7.5
Additional-Program Data Computation Table
Verify Data 0 1 0 1 Additional-Program Data 0 1 1 1 Comments Additional-program bit No additional programming No additional programming No additional programming
Reprogram Data 0 0 1 1
Table 7.6
Programming Time
Programming Time 30 200 In Additional Programming 10 -- Comments
n (Number of Writes) 1 to 6 7 to 1,000
Note: Time shown in s.
7.4.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed.
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Section 7 ROM
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
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Section 7 ROM
Erase start SWE bit 1 Wait 1 s n1 Set EBR1 Enable WDT ESU bit 1 Wait 100 s E bit 1 Wait 10 ms E bit 0 Wait 10 s ESU bit 10 10 s Disable WDT EV bit 1 Wait 20 s
Set block start address as verify address
H'FF dummy write to verify address Wait 2 s Read verify data No Increment address Verify data + all 1s ? Yes No Last address of block ? Yes EV bit 0 Wait 4 s EV bit 0 Wait 4s
*
nn+1
No
All erase block erased ? Yes Yes SWE bit 0 Wait 100 s End of erasing
n 100 ? No
Yes
SWE bit 0 Wait 100 s Erase failure
Note: * The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
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Section 7 ROM
7.5
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 7.5.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00, erase protection is set for all blocks. 7.5.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling excluding a reset during programming/erasing * When a SLEEP instruction is executed during programming/erasing
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Section 7 ROM
The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset.
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Section 8 RAM
Section 8 RAM
This LSI has 2 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification Flash memory version H8/36024F, H8/36014F H8/36022F, H8/36012F Masked ROM version H8/36024, H8/36014 H8/36023, H8/36013 H8/36022, H8/36012 H8/36011 H8/36010 Note: * RAM Size 2 kbytes 2 kbytes 1 kbyte 1 kbyte 512 bytes 512 bytes 512 bytes RAM Address H'F780 to H'FF7F* H'F780 to H'FF7F* H'FB80 to H'FF7F H'FB80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F H'FD80 to H'FF7F
When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed.
RAM0400A_000020020200
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Section 8 RAM
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Section 9 I/O Ports
Section 9 I/O Ports
The group of this LSI has thirty general I/O ports and four general input-only ports. Port 8 is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. The registers for selecting these functions can be divided into two types: those included in I/O ports and those included in each on-chip peripheral module. General I/O ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. For functions in each port, see Appendix B.1, I/O Port Block Diagrams. For the execution of bit manipulation instructions to the port control register and port data register, see section 2.8.3, Bit Manipulation Instruction.
9.1
Port 1
Port 1 is a general I/O port also functioning as IRQ interrupt input pins, timer V input pin, and SCI3 I/O pin. Figure 9.1 shows its pin configuration.
P17/IRQ3/TRGV P16 P15 Port 1 P14/IRQ0 P12/SCK3_3* P11 P10
Note: * The SCK3_3 pin is not available in the H8/36014.
Figure 9.1 Port 1 Pin Configuration Port 1 has the following registers. * * * * Port mode register 1 (PMR1) Port control register 1 (PCR1) Port data register 1 (PDR1) Port pull-up control register 1 (PUCR1)
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Section 9 I/O Ports
9.1.1
Port Mode Register 1 (PMR1)
PMR1 switches the functions of pins in port 1, port 2, and port 7.
Bit 7 Bit Name IRQ3 Initial Value 0 R/W R/W Description P17/IRQ3/TRGV Pin Function Switch This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6, 5 4 IRQ0 All 0 0 R/W Reserved These bits are always read as 0. P14/IRQ0 Pin Function Switch This bit selects whether pin P14/IRQ0 is used as P14 or as IRQ0. 0: General I/O port 1: IRQ0 input pin 3 TXD2 0 R/W P72/TXD_2 Pin Function Switch This bit selects whether pin P72/TXD_2 is used as P72 or as TXD_2. 0: General I/O port 1: TXD_2 output pin 2 0 R/W Reserved This bit must always be cleared to 0 (setting to 1 is disabled). 1 TXD 0 R/W P22/TXD Pin Function Switch This bit selects whether pin P22/TXD is used as P22 or as TXD. 0: General I/O port 1: TXD output pin 0 0 Reserved This bit is always read as 0.
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Section 9 I/O Ports
9.1.2
Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR17 PCR16 PCR15 PCR14 PCR12 PCR11 PCR10 Initial Value 0 0 0 0 0 0 0 R/W W W W W W W W Description When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Bit 3 is a reserved bit.
9.1.3
Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name P17 P16 P15 P14 P12 P11 P10 Initial Value 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description PDR1 stores output data for port 1 pins. If PDR1 is read while PCR1 bits are set to 1, the value stored in PDR1 are read. If PDR1 is read while PCR1 bits are cleared to 0, the pin states are read regardless of the value stored in PDR1. Bit 3 is a reserved bit. This bit is always read as 1.
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Section 9 I/O Ports
9.1.4
Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR17 PUCR16 PUCR15 PUCR14 PUCR12 PUCR11 PUCR10 Initial Value 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Only bits for which PCR1 is cleared are valid. The pull-up MOS of P17 to P14 and P12 to P10 pins enter the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. Bit 3 is a reserved bit. This bit is always read as 1.
9.1.5
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P17/IRQ3/TRGV pin
Register Bit Name PMR1 IRQ3 PCR1 PCR17 0 1 1 Legend X: Don't care. X Pin Function P17 input pin P17 output pin IRQ3 input/TRGV input pin
Setting value 0
* P16 pin
Register Bit Name Setting value PCR1 PCR16 0 1 Pin Function P16 input pin P16 output pin
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Section 9 I/O Ports
* P15 pin
Register Bit Name Setting value PCR1 PCR15 0 1 Pin Function P15 input pin P15 output pin
* P14/IRQ0 pin
Register Bit Name PMR1 IRQ0 PCR1 PCR14 0 1 1 Legend X: Don't care. X Pin Function P14 input pin P14 output pin IRQ0 input pin
Setting value 0
* P12/SCK3_3* pin
Register Bit Name Setting value SCR3_3* CKE1 0 CKE0 0 SMR_3* PCR1 COM 0 PCR12 0 1 1 0 1 1 X X X X X X Pin Function P12 input pin P12 output pin SCK3_3 output pin* SCK3_3 output pin* SCK3_3 input pin*
Legend X: Don't care. Note: * Not available in the H8/36014.
* P11 pin
Register Bit Name Setting value PCR1 PCR11 0 1 Pin Function P11 input pin P11 output pin
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Section 9 I/O Ports
* P10 pin
Register Bit Name Setting value PCR1 PCR10 0 1 Pin Function P10 input pin P10 output pin
9.2
Port 2
Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses.
P22/TXD Port 2 P21/RXD P20/SCK3
Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. * Port control register 2 (PCR2) * Port data register 2 (PDR2) 9.2.1 Port Control Register 2 (PCR2)
PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2.
Bit 7 to 3 2 1 0 Bit Name PCR22 PCR21 PCR20 Initial Value 0 0 0 R/W W W W Description Reserved When each of the port 2 pins P22 to P20 functions as an general I/O port, setting a PCR2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
9.2.2
Port Data Register 2 (PDR2)
PDR2 is a general I/O port data register of port 2.
Bit 7 to 3 2 1 0 Bit Name P22 P21 P20 Initial Value All 1 0 0 0 R/W R/W R/W R/W Description Reserved These bits are always read as 1. PDR2 stores output data for port 2 pins. If PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read. If PDR2 is read while PCR2 bits are cleared to 0, the pin states are read regardless of the value stored in PDR2.
9.2.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P22/TXD pin
Register Bit Name PMR1 TXD PCR2 PCR22 0 1 1 Legend X: Don't care. X Pin Function P22 input pin P22 output pin TXD output pin
Setting Value 0
* P21/RXD pin
Register Bit Name SCR3 RE PCR2 PCR21 0 1 1 Legend X: Don't care. X Pin Function P21 input pin P21 output pin RXD input pin
Setting Value 0
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Section 9 I/O Ports
* P20/SCK3 pin
Register Bit Name Setting Value SCR3 CKE1 0 CKE0 0 SMR COM 0 PCR2 PCR20 0 1 0 0 1 Legend X: Don't care. 0 1 X 1 X X X X X Pin Function P20 input pin P20 output pin SCK3 output pin SCK3 output pin SCK3 input pin
9.3
Port 5
Port 5 is a general I/O port also functioning as an SCI3 I/O pins, A/D trigger input pin, and wakeup interrupt input pins. Each pin of the port 5 is shown in figure 9.3.
P57/TXD_3* P56/RXD_3* P55/WKP5/ADTRG Port 5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0
Note: * The TXD_3 and RXD_3 pins are not available in the H8/36014.
Figure 9.3 Port 5 Pin Configuration Port 5 has the following registers. * * * * Port mode register 5 (PMR5) Port control register 5 (PCR5) Port data register 5 (PDR5) Port pull-up control register 5 (PUCR5)
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Section 9 I/O Ports
9.3.1
Port Mode Register 5 (PMR5)
PMR5 switches the functions of pins in port 5.
Bit 7 Bit Name POF57 Initial Value 0 R/W R/W Description P57 Pin Function Switch 0: General I/O port 1: NMOS open-drain output 6 POF56 0 R/W P56 Pin Function Switch 0: General I/O port 1: NMOS open-drain output 5 WKP5 0 R/W P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG input. 0: General I/O port 1: WKP5/ADTRG input pin 4 WKP4 0 R/W P54/WKP4 Pin Function Switch Selects whether pin P54/WKP4 is used as P54 or as WKP4. 0: General I/O port 1: WKP4 input pin 3 WKP3 0 R/W P53/WKP3 Pin Function Switch Selects whether pin P53/WKP3 is used as P53 or as WKP3. 0: General I/O port 1: WKP3 input pin 2 WKP2 0 R/W P52/WKP2 Pin Function Switch Selects whether pin P52/WKP2 is used as P52 or as WKP2. 0: General I/O port 1: WKP2 input pin 1 WKP1 0 R/W P51/WKP1 Pin Function Switch Selects whether pin P51/WKP1 is used as P51 or as WKP1. 0: General I/O port 1: WKP1 input pin
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Section 9 I/O Ports
Bit 0
Bit Name WKP0
Initial Value 0
R/W R/W
Description P50/WKP0 Pin Function Switch Selects whether pin P50/WKP0 is used as P50 or as WKP0. 0: General I/O port 1: WKP0 input pin
9.3.2
Port Control Register 5 (PCR5)
PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When each of the port 5 pins P57 to P50 functions as an general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
9.3.3
Port Data Register 5 (PDR5)
PDR5 is a general I/O port data register of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Stores output data for port 5 pins. If PDR5 is read while PCR5 bits are set to 1, the value stored in PDR5 are read. If PDR5 is read while PCR5 bits are cleared to 0, the pin states are read regardless of the value stored in PDR5.
9.3.4
Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit 7, 6 5 4 3 2 1 0 Bit Name PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial Value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. Only bits for which PCR5 is cleared are valid. The pull-up MOS of the corresponding pins enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0.
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Section 9 I/O Ports
9.3.5
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P57/TXD_3* pin
Register Bit Name SMCR* TXD_3 PCR5 PCR57 0 1 1 X Legend X: Don't care. Note: * Not available in the H8/36014. Pin Function P57 input pin P57 output pin TXD_3 output pin*
Setting Value 0
* P56/RXD_3* pin
Register Bit Name SCR3_3* RE PCR5 PCR56 0 1 1 X Legend X: Don't care. Note: * Not available in the H8/36014. Pin Function P56 input pin P56 output pin RXD_3 input pin*
Setting Value 0
* P55/WKP5/ADTRG pin
Register Bit Name PMR5 WKP5 PCR5 PCR55 0 1 1 Legend X: Don't care. X Pin Function P55 input pin P55 output pin WKP5/ADTRG input pin
Setting Value 0
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Section 9 I/O Ports
* P54/WKP4 pin
Register Bit Name PMR5 WKP4 PCR5 PCR54 0 1 1 Legend X: Don't care. X Pin Function P54 input pin P54 output pin WKP4 input pin
Setting Value 0
* P53/WKP3 pin
Register Bit Name PMR5 WKP3 PCR5 PCR53 0 1 1 Legend X: Don't care. X Pin Function P53 input pin P53 output pin WKP3 input pin
Setting Value 0
* P52/WKP2 pin
Register Bit Name PMR5 WKP2 PCR5 PCR52 0 1 1 Legend X: Don't care. X Pin Function P52 input pin P52 output pin WKP2 input pin
Setting Value 0
* P51/WKP1 pin
Register Bit Name PMR5 WKP1 PCR5 PCR51 0 1 1 Legend X: Don't care. X Pin Function P51 input pin P51 output pin WKP1 input pin
Setting Value 0
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Section 9 I/O Ports
* P50/WKP0 pin
Register Bit Name PMR5 WKP0 PCR5 PCR50 0 1 1 Legend X: Don't care. X Pin Function P50 input pin P50 output pin WKP0 input pin
Setting Value 0
9.4
Port 7
Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4. The register setting of TCSRV in timer V has priority for functions of pin P76/TMOV. The pins, P75/TMCIV and P74/TMRIV, are also functioning as timer V input ports that are connected to the timer V regardless of the register setting of port 7.
P76/TMOV P75/TMCIV P74/TMRIV Port 7 P73 P72/TXD_2 P71/SCK3_2 P70/SCK3_2
Figure 9.4 Port 7 Pin Configuration Port 7 has the following registers. * Port control register 7 (PCR7) * Port data register 7 (PDR7)
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Section 9 I/O Ports
9.4.1
Port Control Register 7 (PCR7)
PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 Initial Value 0 0 0 0 0 0 0 R/W W W W W W W W Description Reserved Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Note that the TCSRV setting of the timer V has priority for deciding input/output direction of the P76/TMOV pin.
9.4.2
Port Data Register 7 (PDR7)
PDR7 is a general I/O port data register of port 7.
Bit 7 6 5 4 3 2 1 0 Bit Name P76 P75 P74 P73 P72 P71 P70 Initial Value 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved This bit is always read as 1. PDR7 stores output data for port 7 pins. If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 is read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7.
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Section 9 I/O Ports
9.4.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P76/TMOV pin
Register Bit Name TCSRV PCR7 Pin Function P76 input pin P76 output pin TMOV output pin
OS3 to OS0 PCR76 0 1 Other than the above values X
Setting Value 0000
Legend X: Don't care.
* P75/TMCIV pin
Register Bit Name PCR7 PCR75 Pin Function P75 input/TMCIV input pin P75 output/TMCIV input pin
Setting Value 0 1
* P74/TMRIV pin
Register Bit Name PCR7 PCR74 Pin Function P74 input/TMRIV input pin P74 output/TMRIV input pin
Setting Value 0 1
* P73 pin
Register Bit Name PCR7 PCR73 Pin Function P73 input pin P73 output pin
Setting Value 0 1
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Section 9 I/O Ports
* P72/TXD_2 pin
Register Bit Name PMR1 TXD2 PCR7 PCR72 0 1 1 Legend X: Don't care. X Pin Function P72 input pin P72 output pin TXD_2 output pin
Setting Value 0
* P71/RXD_2 pin
Register Bit Name SCR3_2 RE PCR7 PCR71 0 1 1 Legend X: Don't care. X Pin Function P71 input pin P71 output pin RXD_2 input pin
Setting Value 0
* P70/SCK3_2 pin
Register Bit Name SCR3_2 CKE1 CKE0 0 SMR_2 COM 0 PCR7 PCR70 0 1 1 0 1 Legend X: Don't care. 1 X X X X X X Pin Function P70 input pin P70 output pin SCK3_2 output pin SCK3_2 output pin SCK3_2 input pin
Setting Value 0
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Section 9 I/O Ports
9.5
Port 8
Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA. The P80/FTCI pin also functions as a timer W input port that is connected to the timer W regardless of the register setting of port 8.
P84/FTIOD P83/FTIOC Port 8 P82/FTIOB P81/FTIOA P80/FTCI
Figure 9.5 Port 8 Pin Configuration Port 8 has the following registers. * Port control register 8 (PCR8) * Port data register 8 (PDR8) 9.5.1 Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit 7 to 5 4 3 2 1 0 Bit Name PCR84 PCR83 PCR82 PCR81 PCR80 Initial Value 0 0 0 0 0 R/W W W W W W Description Reserved When each of the port 8 pins P84 to P80 functions as an general I/O port, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
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Section 9 I/O Ports
9.5.2
Port Data Register 8 (PDR8)
PDR8 is a general I/O port data register of port 8.
Bit 7 to 5 4 3 2 1 0 Bit Name P84 P83 P82 P81 P80 Initial Value All 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Reserved PDR8 stores output data for port 8 pins. If PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8.
9.5.3
Pin Functions
The correspondence between the register specification and the port functions is shown below. * P84/FTIOD pin
Register Bit Name TIOR1 IOD2 IOD1 0 IOD0 0 PCR8 PCR84 0 1 0 0 1 Legend X: Don't care. 0 1 X 1 X X X X 0 1 Pin Function P84 input/FTIOD input pin P84 output/FTIOD input pin FTIOD output pin FTIOD output pin P84 input/FTIOD input pin P84 output/FTIOD input pin
Setting Value 0
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Section 9 I/O Ports
* P83/FTIOC pin
Register Bit Name TIOR1 IOC2 IOC1 0 IOC0 0 PCR8 PCR83 0 1 0 0 1 Legend X: Don't care. 0 1 X 1 X X X X 0 1 Pin Function P83 input/FTIOC input pin P83 output/FTIOC input pin FTIOC output pin FTIOC output pin P83 input/FTIOC input pin P83 output/FTIOC input pin
Setting Value 0
* P82/FTIOB pin
Register Bit Name TIOR0 IOB2 IOB1 0 IOB0 0 PCR8 PCR82 0 1 0 0 1 Legend X: Don't care. 0 1 X 1 X X X X 0 1 Pin Function P82 input/FTIOB input pin P82 output/FTIOB input pin FTIOB output pin FTIOB output pin P82 input/FTIOB input pin P82 output/FTIOB input pin
Setting Value 0
* P81/FTIOA pin
Register Bit Name TIOR0 IOA2 IOA1 0 IOA0 0 PCR8 PCR81 0 1 0 0 1 Legend X: Don't care. 0 1 X 1 X X X X 0 1 Pin Function P81 input/FTIOA input pin P81 output/FTIOA input pin FTIOA output pin FTIOA output pin P81 input/FTIOA input pin P81 output/FTIOA input pin
Setting Value 0
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Section 9 I/O Ports
* P80/FTCI pin
Register Bit Name PCR8 PCR80 Pin Function P80 input/FTCI input pin P80 output/FTCI input pin
Setting Value 0 1
9.6
Port B
Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6.
PB3/AN3 Port B PB2/AN2 PB1/AN1 PB0/AN0
Figure 9.6 Port B Pin Configuration Port B has the following register. * Port data register B (PDRB)
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Section 9 I/O Ports
9.6.1
Port Data Register B (PDRB)
PDRB is a general input-only port data register of port B.
Bit 7 to 4 3 2 1 0 Bit Name PB3 PB2 PB1 PB0 Initial Value R/W R R R R Description Reserved The input value of each pin is read by reading this register. However, if a port B pin is designated as an analog input channel by ADCSR in A/D converter, 0 is read.
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Section 10 Timer V
Section 10 Timer V
Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 10.1 shows a block diagram of timer V.
10.1
Features
* Choice of seven clock signals is available. Choice of six internal clock sources (/128, /64, /32, /16, /8, /4) or an external clock. * Counter can be cleared by compare match A or B, or by an external reset signal. If the count stop function is selected, the counter can be halted when cleared. * Timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, PWM output, and other applications. * Three interrupt sources: compare match A, compare match B, timer overflow * Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or both edges of the TRGV input can be selected.
TIM08V0A_000120030300
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Section 10 Timer V
TCRV1
TCORB TRGV Trigger control Comparator
Comparator o PSS TCORA Clear control
TMRIV
TCRV0 Interrupt request control
TMOV
Output control
TCSRV CMIA CMIB OVI
Legend: TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI:
Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B Overflow interupt
Figure 10.1 Block Diagram of Timer V
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Internal data bus
TMCIV
Clock select
TCNTV
Section 10 Timer V
10.2
Input/Output Pins
Table 10.1 shows the timer V pin configuration. Table 10.1 Pin Configuration
Name Timer V output Timer V clock input Timer V reset input Trigger input Abbreviation I/O TMOV TMCIV TMRIV TRGV Output Input Input Input Function Timer V waveform output Clock input to TCNTV External input to reset TCNTV Trigger input to initiate counting
10.3
Register Descriptions
Time V has the following registers. * * * * * * Timer counter V (TCNTV) Timer constant register A (TCORA) Timer constant register B (TCORB) Timer control register V0 (TCRV0) Timer control/status register V (TCSRV) Timer control register V1 (TCRV1) Timer Counter V (TCNTV)
10.3.1
TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time. TCNTV can be cleared by an external reset input signal, or by compare match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0. When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV). TCNTV is initialized to H'00.
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Section 10 Timer V
10.3.2
Time Constant Registers A and B (TCORA, TCORB)
TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle. Timer output from the TMOV pin can be controlled by the identifying signal (compare match A) and the settings of bits OS3 to OS0 in TCSRV. TCORA and TCORB are initialized to H'FF.
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Section 10 Timer V
10.3.3
Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request.
Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled. 6 CMIEA 0 R/W Compare Match Interrupt Enable A When this bit is set to 1, interrupt request from the CMFA bit in TCSRV is enabled. 5 OVIE 0 R/W Timer Overflow Interrupt Enable When this bit is set to 1, interrupt request from the OVF bit in TCSRV is enabled. 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1 and 0 These bits specify the clearing conditions of TCNTV. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared on the rising edge of the TMRIV pin. The operation of TCNTV after clearing depends on TRGE in TCRV1. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select clock signals to input to TCNTV and the counting condition in combination with ICKS0 in TCRV1. Refer to table 10.2.
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Section 10 Timer V
Table 10.2 Clock Signals to Input to TCNTV and Counting Conditions
TCRV0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 TCRV1 Bit 0 ICKS0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 Description Clock input prohibited Internal clock: counts on /4, falling edge Internal clock: counts on /8, falling edge Internal clock: counts on /16, falling edge Internal clock: counts on /32, falling edge Internal clock: counts on /64, falling edge Internal clock: counts on /128, falling edge Clock input prohibited External clock: counts on rising edge External clock: counts on falling edge External clock: counts on rising and falling edge
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Section 10 Timer V
10.3.4
Timer Control/Status Register V (TCSRV)
TCSRV indicates the status flag and controls outputs by using a compare match.
Bit 7 Bit Name CMFB Initial Value 0 R/W R/W Description Compare Match Flag B Setting condition: When the TCNTV value matches the TCORB value Clearing condition: After reading CMFB = 1, cleared by writing 0 to CMFB 6 CMFA 0 R/W Compare Match Flag A Setting condition: When the TCNTV value matches the TCORA value Clearing condition: After reading CMFA = 1, cleared by writing 0 to CMFA 5 OVF 0 R/W Timer Overflow Flag Setting condition: When TCNTV overflows from H'FF to H'00 Clearing condition: After reading OVF = 1, cleared by writing 0 to OVF 4 3 2 OS3 OS2 1 0 0 R/W R/W Reserved This bit is always read as 1. Output Select 3 and 2 These bits select an output method for the TMOV pin by the compare match of TCORB and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles
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Section 10 Timer V
Bit 1 0
Bit Name OS1 OS0
Initial Value 0 0
R/W R/W R/W
Description Output Select 1 and 0 These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match.
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Section 10 Timer V
10.3.5
Timer Control Register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV.
Bit 7 to 5 4 3 Bit Name TVEG1 TVEG0 Initial Value All 1 0 0 R/W R/W R/W Description Reserved These bits are always read as 1. TRGV Input Edge Select These bits select the TRGV input edge. 00: TRGV trigger input is prohibited 01: Rising edge is selected 10: Falling edge is selected 11: Rising and falling edges are both selected 2 TRGE 0 R/W TCNT starts counting up by the input of the edge which is selected by TVEG1 and TVEG0. 0: Disables starting counting-up TCNTV by the input of the TRGV pin and halting counting-up TCNTV when TCNTV is cleared by a compare match. 1: Enables starting counting-up TCNTV by the input of the TRGV pin and halting counting-up TCNTV when TCNTV is cleared by a compare match. 1 0 ICKS0 1 0 R/W Reserved This bit is always read as 1. Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 10.2.
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Section 10 Timer V
10.4
10.4.1
Operation
Timer V Operation
1. According to table 10.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 10.2 shows the count timing with an internal clock signal selected, and figure 10.3 shows the count timing with both edges of an external clock signal selected. 2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0 will be set. The timing at this time is shown in figure 10.4. An interrupt request is sent to the CPU when OVIE in TCRV0 is 1. 3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The compare-match signal is generated in the last state in which the values match. Figure 10.5 shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in TCRV0 is 1. 4. When a compare match A or B is generated, the TMOV responds with the output value selected by bits OS3 to OS0 in TCSRV. Figure 10.6 shows the timing when the output is toggled by compare match A. 5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding compare match. Figure 10.7 shows the timing. 6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary. Figure 10.8 shows the timing. 7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.
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Section 10 Timer V
o
Internal clock
TCNTV input clock
TCNTV
N-1
N
N+1
Figure 10.2 Increment Timing with Internal Clock
o TMCIV (External clock input pin) TCNTV input clock
TCNTV
N-1
N
N+1
Figure 10.3 Increment Timing with External Clock
o TCNTV H'FF H'00
Overflow signal
OVF
Figure 10.4 OVF Set Timing
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Section 10 Timer V
o TCNTV N N+1
TCORA or TCORB Compare match signal CMFA or CMFB
N
Figure 10.5 CMFA and CMFB Set Timing
o
Compare match A signal
Timer V output pin
Figure 10.6 TMOV Output Timing
o
Compare match A signal
TCNTV
N
H'00
Figure 10.7 Clear Timing by Compare Match
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Section 10 Timer V
o
TMRIV(External counter reset input pin ) TCNTV reset signal
TCNTV
N-1
N
H'00
Figure 10.8 Clear Timing by TMRIV Input
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Section 10 Timer V
10.5
10.5.1
Timer V Application Examples
Pulse Output with Arbitrary Duty Cycle
Figure 10.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 4. With these settings, a waveform is output without further software intervention, with a period determined by TCORA and a pulse width determined by TCORB.
TCNTV value H'FF Counter cleared TCORA TCORB H'00
TMOV
Time
Figure 10.9 Pulse Output Example
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Section 10 Timer V
10.5.2
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 10.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV input. 4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 5. After these settings, a pulse waveform will be output without further software intervention, with a delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB - TCORA).
TCNTV value H'FF Counter cleared TCORB TCORA H'00 TRGV Time
TMOV
Compare match A Compare match A
Compare match B clears TCNTV and halts count-up
Compare match B clears TCNTV and halts count-up
Figure 10.10 Example of Pulse Output Synchronized to TRGV Input
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Section 10 Timer V
10.6
Usage Notes
The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 10.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 10.12 shows the timing. If compare matches A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by the following priority: toggle output > output 1 > output 0. Depending on the timing, TCNTV may be incremented by a switch between different internal clock sources. When TCNTV is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, that is divided system clock (). Therefore, as shown in figure 10.3 the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a switch between internal and external clocks.
TCNTV write cycle by CPU T1 T2 T3
2.
3.
4.
o
Address
TCNTV address
Internal write signal
Counter clear signal
TCNTV
N
H'00
Figure 10.11 Contention between TCNTV Write and Clear
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Section 10 Timer V
TCORA write cycle by CPU T1 T2 T3
o
Address
TCORA address
Internal write signal
TCNTV
N
N+1
TCORA
N
M TCORA write data
Compare match signal Inhibited
Figure 10.12 Contention between TCORA Write and Compare Match
Clock before switching
Clock after switching
Count clock
TCNTV
N
N+1
N+2
Write to CKS1 and CKS0
Figure 10.13 Internal Clock Switching and TCNTV Operation
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Section 10 Timer V
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Section 11 Timer W
Section 11 Timer W
The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems.
11.1
Features
* Selection of five counter clock sources: four internal clocks (, /2, /4, and /8) and an external clock (external events can be counted) * Capability to process up to four pulse outputs or four pulse inputs * Four general registers: Independently assignable output compare or input capture functions Usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register * Four selectable operating modes : Waveform output by compare match Selection of 0 output, 1 output, or toggle output Input capture function Rising edge, falling edge, or both edges Counter clearing function Counters can be cleared by compare match PWM mode Up to three-phase PWM output can be provided with desired duty ratio. * Any initial timer output value can be set * Five interrupt sources Four compare match/input capture interrupts and an overflow interrupt. Table 11.1 summarizes the timer W functions, and figure 11.1 shows a block diagram of the timer W.
TIM08W0A_000020020200
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Section 11 Timer W
Table 11.1 Timer W Functions
Input/Output Pins Item Count clock General registers (output compare/input capture registers) Counter clearing function Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: , /2, /4, /8 External clock: FTCI Period GRA specified in GRA GRA compare match -- -- 0 1 Toggle Input capture function PWM mode Interrupt sources -- -- -- -- -- Overflow GRA compare match Yes Yes Yes Yes Yes Yes -- Compare match/input capture GRB GRC (buffer register for GRA in buffer mode) -- GRD (buffer register for GRB in buffer mode) --
--
Initial output value setting function Buffer function Compare match output
Yes Yes Yes Yes Yes Yes Yes Compare match/input capture
Yes -- Yes Yes Yes Yes Yes Compare match/input capture
Yes -- Yes Yes Yes Yes Yes Compare match/input capture
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Section 11 Timer W
Internal clock: o o/2 o/4 o/8 External clock: FTCI
FTIOA Clock selector Control logic Comparator FTIOB FTIOC FTIOD IRRTW
TIERW
TMRW
TCRW
TSRW
TCNT
TIOR
GRC
GRD
GRA
GRB
Legend: TMRW: TCRW: TIERW: TSRW: TIOR: TCNT: GRA: GRB: GRC: GRD: IRRTW:
Timer mode register W (8 bits) Timer control register W (8 bits) Timer interrupt enable register W (8 bits) Timer status register W (8 bits) Timer I/O control register (8 bits) Timer counter (16 bits) General register A (input capture/output compare register: 16 bits) General register B (input capture/output compare register: 16 bits) General register C (input capture/output compare register: 16 bits) General register D (input capture/output compare register: 16 bits) Timer W interrupt request
Figure 11.1 Timer W Block Diagram
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Bus interface
Internal data bus
Section 11 Timer W
11.2
Input/Output Pins
Table 11.2 summarizes the timer W pins. Table 11.2 Pin Configuration
Name External clock input Input capture/output compare A Input capture/output compare B Input capture/output compare C Input capture/output compare D Abbreviation FTCI FTIOA FTIOB Input/Output Input Input/output Input/output Function External clock input pin Output pin for GRA output compare or input pin for GRA input capture Output pin for GRB output compare, input pin for GRB input capture, or PWM output pin in PWM mode Output pin for GRC output compare, input pin for GRC input capture, or PWM output pin in PWM mode Output pin for GRD output compare, input pin for GRD input capture, or PWM output pin in PWM mode
FTIOC
Input/output
FTIOD
Input/output
11.3
Register Descriptions
The timer W has the following registers. * * * * * * * * * * * Timer mode register W (TMRW) Timer control register W (TCRW) Timer interrupt enable register W (TIERW) Timer status register W (TSRW) Timer I/O control register 0 (TIOR0) Timer I/O control register 1 (TIOR1) Timer counter (TCNT) General register A (GRA) General register B (GRB) General register C (GRC) General register D (GRD)
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Section 11 Timer W
11.3.1
Timer Mode Register W (TMRW)
TMRW selects the general register functions and the timer output mode.
Bit 7 Bit Name CTS Initial Value 0 R/W R/W Description Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 5 BUFEB 1 0 R/W Reserved This bit is always read as 1. Buffer Operation B Selects the GRD function. 0: GRD operates as an input capture/output compare register 1: GRD operates as the buffer register for GRB 4 BUFEA 0 R/W Buffer Operation A Selects the GRC function. 0: GRC operates as an input capture/output compare register 1: GRC operates as the buffer register for GRA 3 2 PWMD 1 0 R/W Reserved This bit is always read as 1. PWM Mode D Selects the output mode of the FTIOD pin. 0: FTIOD operates normally (output compare output) 1: PWM output 1 PWMC 0 R/W PWM Mode C Selects the output mode of the FTIOC pin. 0: FTIOC operates normally (output compare output) 1: PWM output 0 PWMB 0 R/W PWM Mode B Selects the output mode of the FTIOB pin. 0: FTIOB operates normally (output compare output) 1: PWM output
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Section 11 Timer W
11.3.2
Timer Control Register W (TCRW)
TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels.
Bit 7 Bit Name CCLR Initial Value 0 R/W R/W Description Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. 6 5 4 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Select the TCNT clock source. 000: Internal clock: counts on 001: Internal clock: counts on /2 010: Internal clock: counts on /4 011: Internal clock: counts on /8 1XX: Counts on rising edges of the external event (FTCI) When the internal clock source () is selected, subclock sources are counted in subactive and subsleep modes. 3 TOD 0 R/W Timer Output Level Setting D Sets the output value of the FTIOD pin until the first compare match D is generated. 0: Output value is 0* 1: Output value is 1* 2 TOC 0 R/W Timer Output Level Setting C Sets the output value of the FTIOC pin until the first compare match C is generated. 0: Output value is 0* 1: Output value is 1* 1 TOB 0 R/W Timer Output Level Setting B Sets the output value of the FTIOB pin until the first compare match B is generated. 0: Output value is 0* 1: Output value is 1*
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Section 11 Timer W
Bit 0
Bit Name TOA
Initial Value 0
R/W R/W
Description Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1*
Legend X: Don't care. Note: * The change of the setting is immediately reflected in the output value.
11.3.3
Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit 7 Bit Name OVIE Initial Value 0 R/W R/W Description Timer Overflow Interrupt Enable When this bit is set to 1, FOVI interrupt requested by OVF flag in TSRW is enabled. 6 to 4 3 IMIED All 1 0 R/W Reserved These bits are always read as 1. Input Capture/Compare Match Interrupt Enable D When this bit is set to 1, IMID interrupt requested by IMFD flag in TSRW is enabled. 2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C When this bit is set to 1, IMIC interrupt requested by IMFC flag in TSRW is enabled. 1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B When this bit is set to 1, IMIB interrupt requested by IMFB flag in TSRW is enabled. 0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A When this bit is set to 1, IMIA interrupt requested by IMFA flag in TSRW is enabled.
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Section 11 Timer W
11.3.4
Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit 7 Bit Name OVF Initial Value 0 R/W R/W Description Timer Overflow Flag [Setting condition] When TCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 to 4 3 IMFD All 1 0 R/W Reserved These bits are always read as 1. Input Capture/Compare Match Flag D [Setting conditions] * * TCNT = GRD when GRD functions as an output compare register The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register
[Clearing condition] Read IMFD when IMFD = 1, then write 0 in IMFD 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] * * TCNT = GRC when GRC functions as an output compare register The TCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register
[Clearing condition] Read IMFC when IMFC = 1, then write 0 in IMFC
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Section 11 Timer W
Bit 1
Bit Name IMFB
Initial Value 0
R/W R/W
Description Input Capture/Compare Match Flag B [Setting conditions] * * TCNT = GRB when GRB functions as an output compare register The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register
[Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] * * TCNT = GRA when GRA functions as an output compare register The TCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register
[Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA
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Section 11 Timer W
11.3.5
Timer I/O Control Register 0 (TIOR0)
TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins.
Bit 7 6 Bit Name IOB2 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control B2 Selects the GRB function. 0: GRB functions as an output compare register 1: GRB functions as an input capture register 5 4 IOB1 IOB0 0 0 R/W R/W I/O Control B1 and B0 When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture at rising edge at the FTIOB pin 01: Input capture at falling edge at the FTIOB pin 1X: Input capture at rising and falling edges of the FTIOB pin 3 2 IOA2 1 0 R/W Reserved This bit is always read as 1. I/O Control A2 Selects the GRA function. 0: GRA functions as an output compare register 1: GRA functions as an input capture register
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Section 11 Timer W
Bit 1 0
Bit Name IOA1 IOA0
Initial Value 0 0
R/W R/W R/W
Description I/O Control A1 and A0 When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1, 00: Input capture at rising edge of the FTIOA pin 01: Input capture at falling edge of the FTIOA pin 1X: Input capture at rising and falling edges of the FTIOA pin
Legend X: Don't care.
11.3.6
Timer I/O Control Register 1 (TIOR1)
TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins.
Bit 7 6 Bit Name IOD2 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control D2 Selects the GRD function. 0: GRD functions as an output compare register 1: GRD functions as an input capture register
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Section 11 Timer W
Bit 5 4
Bit Name IOD1 IOD0
Initial Value 0 0
R/W R/W R/W
Description I/O Control D1 and D0 When IOD2 = 0, 00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD2 = 1, 00: Input capture at rising edge at the FTIOD pin 01: Input capture at falling edge at the FTIOD pin 1X: Input capture at rising and falling edges at the FTIOD pin
3 2
IOC2
1 0
R/W
Reserved This bit is always read as 1. I/O Control C2 Selects the GRC function. 0: GRC functions as an output compare register 1: GRC functions as an input capture register
1 0
IOC1 IOC0
0 0
R/W R/W
I/O Control C1 and C0 When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1X: Input capture to GRC at rising and falling edges of the FTIOC pin
Legend X: Don't care.
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Section 11 Timer W
11.3.7
Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed. TCNT is initialized to H'0000 by a reset. 11.3.8 General Registers A to D (GRA to GRD)
Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1. When a general register is used as an input-compare register, its value is constantly compared with the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR. When a general register is used as an input-capture register, an external input-capture signal is detected and the current TCNT value is stored in the general register. The corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit (IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is generated. The edge of the input-capture signal is selected in TIOR. GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TMRW. For example, when GRA is set as an output-compare register and GRC is set as the buffer register for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is generated. When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the value in TCNT is transferred to GRA and the value in the buffer register GRC is transferred to GRA whenever an input capture is generated. GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are initialized to H'FFFF by a reset.
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Section 11 Timer W
11.4
Operation
The timer W has the following operating modes. * Normal Operation * PWM Operation 11.4.1 Normal Operation
TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 11.2 shows free-running counting.
TCNT value H'FFFF
H'0000 CTS bit
Time
Flag cleared by software
OVF
Figure 11.2 Free-Running Counter Operation
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Section 11 Timer W
Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated. TCNT continues counting from H'0000. Figure 11.3 shows periodic counting.
TCNT value GRA
H'0000 CTS bit
Flag cleared by software
Time
IMFA
Figure 11.3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 11.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B. When signal is already at the selected output level, the signal level does not change at compare match.
TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB No change No change Time No change No change
Figure 11.4 0 and 1 Output Example (TOA = 0, TOB = 1)
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Section 11 Timer W
Figure 11.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B.
TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB Time Toggle output Toggle output
Figure 11.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 11.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B.
TCNT value Counter cleared by compare match with GRA H'FFFF GRA GRB H'0000 FTIOA FTIOB Time Toggle output Toggle output
Figure 11.6 Toggle Output Example (TOA = 0, TOB = 1)
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Section 11 Timer W
The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 11.7 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter.
TCNT value
H'FFFF
H'F000
H'AA55 H'55AA
H'1000 H'0000
Time
FTIOA
GRA
H'1000
H'F000
H'55AA
FTIOB
GRB
H'AA55
Figure 11.7 Input Capture Operating Example
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Section 11 Timer W
Figure 11.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
TCNT value
H'FFFF
H'DA91
H'5480
H'0245 H'0000
FTIOA
Time
GRA
H'0245
H'5480
H'DA91
GRC
H'0245
H'5480
Figure 11.8 Buffer Operation Example (Input Capture)
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Section 11 Timer W
11.4.2
PWM Operation
In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. The output level of each pin depends on the corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode. If the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. Figure 11.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 1: initial output values are set to 1).
TCNT value GRA GRB GRC
GRD
Counter cleared by compare match A
H'0000 FTIOB FTIOC
Time
FTIOD
Figure 11.9 PWM Mode Example (1)
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Section 11 Timer W
Figure 11.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1).
TCNT value GRA GRB GRC
GRD
Counter cleared by compare match A
H'0000 FTIOB FTIOC
Time
FTIOD
Figure 11.10 PWM Mode Example (2)
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Section 11 Timer W
Figure 11.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
TCNT value GRA
H'0200
H'0450
H'0520
GRB
H'0000 GRD
H'0200
H'0450
Time
H'0520
GRB
H'0200
H'0450
H'0520
FTIOB
Figure 11.11 Buffer Operation Example (Output Compare)
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Section 11 Timer W
Figures 11.12 and 11.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%.
TCNT value GRA
Write to GRB
GRB H'0000 Duty 0%
Write to GRB Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB Write to GRB
GRB H'0000 Duty 100% Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously.
Write to GRB Write to GRB Time Duty 100% Duty 0%
GRB H'0000
FTIOB
Figure 11.12 PWM Mode Example (TOB, TOC, and TOD = 0: initial output values are set to 0)
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Section 11 Timer W
TCNT value GRA
Write to GRB
GRB
Write to GRB
H'0000
Duty 100%
Time
FTIOB
TCNT value
Write to GRB
Output does not change when cycle register and duty register compare matches occur simultaneously.
GRA
Write to GRB
Write to GRB
GRB
H'0000
Duty 0%
Time
FTIOB
TCNT value
Write to GRB
Output does not change when cycle register and duty register compare matches occur simultaneously.
GRA
Write to GRB Write to GRB
GRB
H'0000
Duty 0%
Duty 100%
Time
FTIOB
Figure 11.13 PWM Mode Example (TOB, TOC, and TOD = 1: initial output values are set to 1)
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Section 11 Timer W
11.5
11.5.1
Operation Timing
TCNT Count Timing
Figure 11.14 shows the TCNT count timing when the internal clock source is selected. Figure 11.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock () cycles; shorter pulses will not be counted correctly.
Internal clock TCNT input clock TCNT
N
Rising edge
N+1
N+2
Figure 11.14 Count Timing for Internal Clock Source
External clock TCNT input clock TCNT N N+1
N+2
Rising edge
Rising edge
Figure 11.15 Count Timing for External Clock Source
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Section 11 Timer W
11.5.2
Output Compare Output Timing
The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input. Figure 11.16 shows the output compare timing.
TCNT input clock TCNT
N N+1
GRA to GRD Compare match signal FTIOA to FTIOD
N
Figure 11.16 Output Compare Output Timing
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Section 11 Timer W
11.5.3
Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 11.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly.
o Input capture input Input capture signal TCNT GRA to GRD
N-1
N
N+1
N+2
N
Figure 11.17 Input Capture Input Signal Timing 11.5.4 Timing of Counter Clearing by Compare Match
Figure 11.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1.
Compare match signal
TCNT
N
H'0000
GRA
N
Figure 11.18 Timing of Counter Clearing by Compare Match
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Section 11 Timer W
11.5.5
Buffer Operation Timing
Figures 11.19 and 11.20 show the buffer operation timing.
Compare match signal TCNT N N+1
GRC, GRD
M
GRA, GRB
M
Figure 11.19 Buffer Operation Timing (Compare Match)
Input capture signal TCNT
N
N+1
GRA, GRB
M
N
N+1
GRC, GRD
M
N
Figure 11.20 Buffer Operation Timing (Input Capture) 11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a general register, the compare match signal is generated only after the next TCNT clock pulse is input.
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Section 11 Timer W
Figure 11.21 shows the timing of the IMFA to IMFD flag setting at compare match.
TCNT input clock TCNT N N+1
GRA to GRD
Compare match signal
N
IMFA to IMFD
IRRTW
Figure 11.21 Timing of IMFA to IMFD Flag Setting at Compare Match 11.5.7 Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 11.22 shows the timing of the IMFA to IMFD flag setting at input capture.
Input capture signal TCNT N
GRA to GRD
N
IMFA to IMFD
IRRTW
Figure 11.22 Timing of IMFA to IMFD Flag Setting at Input Capture
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Section 11 Timer W
11.5.8
Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 11.23 shows the status flag clearing timing.
TSRW write cycle T1 T2
Address
TSRW address
Write signal
IMFA to IMFD
IRRTW
Figure 11.23 Timing of Status Flag Clearing by CPU
11.6
Usage Notes
The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle. If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 11.24. If counting-up is generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes precedence. 3. Depending on the timing, TCNT may be incremented by a switch between different internal clock sources. When TCNT is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is divided system clock (). Therefore, as shown in figure 11.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing TCNT to increment. 4. If timer W enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. Before entering module standby mode, disable interrupt requests.
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Section 11 Timer W
TCNT write cycle T2 T1
Address
TCNT address
Write signal Counter clear signal
TCNT
N
H'0000
Figure 11.24 Contention between TCNT Write and Clear
Previous clock New clock
Count clock
TCNT
N
N+1
N+2
N+3
The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count.
Figure 11.25 Internal Clock Switching and TCNT Operation
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Section 11 Timer W
5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and the generation of the compare match A to D occur at the same timing, the writing to TCRW has the priority. Thus, output change due to the compare match is not reflected to the FTIOA to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TCRW, the values of the FTIOA to FTIOD pin output may result in an unexpected result. When TCRW is to be written to while compare match is operating, stop the counter once before accessing to TCRW, read the port 8 state to reflect the values of FTIOA to FTIOD output, to TOA to TOD, and then restart the counter. Figure 11.26 shows an example when the compare match and the bit manipulation instruction to TCRW occur at the same timing.
TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B. When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low; the FTIOB signal remains high. Bit TCRW Set value 7 CCLR 0 6 CKS2 0 5 CKS1 0 4 CKS0 0 3 TOD 0 2 TOC 1 1 TOB 1 0 TOA 0
BCLR#2, @TCRW (1) TCRW read operation: Read H'06 (2) Modify operation: Modify H'06 to H'02 (3) Write operation to TCRW: Write H'02
TCRW write signal
Compare match signal B
FTIOB pin Expected output Remains high because the 1 writing to TOB has priority
Figure 11.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing
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Section 11 Timer W
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Section 12 Watchdog Timer
Section 12 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 12.1.
Internal oscillator
CLK
TCSRWD
o
PSS
TCWD
TMWD
Legend: TCSRWD: TCWD: PSS: TMWD:
Timer control/status register WD Timer counter WD Prescaler S Timer mode register WD
Internal reset signal
Figure 12.1 Block Diagram of Watchdog Timer
12.1
Features
* Selectable from nine counter input clocks. Eight clock sources (/64, /128, /256, /512, /1024, /2048, /4096, and /8192) or the internal oscillator can be selected as the timer-counter clock. When the internal oscillator is selected, it can operate as the watchdog timer in any operating mode. * Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set.
WDT0110A_000020020200
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Internal data bus
Section 12 Watchdog Timer
12.2
Register Descriptions
The watchdog timer has the following registers. * Timer control/status register WD (TCSRWD) * Timer counter WD (TCWD) * Timer mode register WD (TMWD) 12.2.1 Timer Control/Status Register WD (TCSRWD)
TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit 7 Bit Name B6WI Initial Value 1 R/W R/W Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0. This bit is always read as 1. 6 TCWE 0 R/W Timer Counter WD Write Enable TCWD can be written when the TCWE bit is set to 1. When writing data to this bit, the value for bit 7 must be 0. 5 B4WI 1 R/W Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1. 4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0. 3 B2WI 1 R/W Bit 2 Write Inhibit This bit can be written to the WDON bit only when the write value of the B2WI bit is 0. This bit is always read as 1.
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Section 12 Watchdog Timer
Bit 2
Bit Name WDON
Initial Value 0
R/W R/W
Description Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0. [Setting condition] When 1 is written to the WDON bit while writing 0 to the B2WI bit when the TCSRWE bit=1 [Clearing condition] * * Reset by RES pin When 0 is written to the WDON bit while writing 0 to the B2WI when the TCSRWE bit=1
1
B0WI
1
R/W
Bit 0 Write Inhibit This bit can be written to the WRST bit only when the write value of the B0WI bit is 0. This bit is always read as 1.
0
WRST
0
R/W
Watchdog Timer Reset [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing condition] * * Reset by RES pin When 0 is written to the WRST bit while writing 0 to the B0WI bit when the TCSRWE bit=1
12.2.2
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00.
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Section 12 Watchdog Timer
12.2.3
Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit 7 to 4 3 2 1 0 Bit Name CKS3 CKS2 CKS1 CKS0 Initial Value All 1 1 1 1 1 R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1. Clock Select 3 to 0 Select the clock to be input to TCWD. 1000: Internal clock: counts on /64 1001: Internal clock: counts on /128 1010: Internal clock: counts on /256 1011: Internal clock: counts on /512 1100: Internal clock: counts on /1024 1101: Internal clock: counts on /2048 1110: Internal clock: counts on /4096 1111: Internal clock: counts on 8192 0XXX: Internal oscillator For the internal oscillator overflow periods, see section 18, Electrical Characteristics. Legend X: Don't care.
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Section 12 Watchdog Timer
12.3
Operation
The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 osc clock cycles. TCWD is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. Figure 12.2 shows an example of watchdog timer operation.
Example: With 30ms overflow period when = 4 MHz 4 x 106 8192 x 30 x 10-3 = 14.6
Therefore, 256 - 15 = 241 (H'F1) is set in TCW.
H'FF
H'F1 TCWD count value
TCWD overflow
H'00
Start H'F1 written to TCWD H'F1 written to TCWD Reset generated
Internal reset signal
256 osc clock cycles
Figure 12.2 Watchdog Timer Operation Example
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Section 12 Watchdog Timer
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Section 13 Serial Communication Interface 3 (SCI3)
Section 13 Serial Communication Interface 3 (SCI3)
This LSI includes a serial communication interface 3 (SCI3). The SCI3 can handle both asynchronous and clocked synchronous serial communication. In asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). Table 13.1 shows the SCI3 channel configuration and figure 13.1 shows a block diagram of the SCI3. Since pin functions are identical for each of the two channels (SCI3 and SCI3_2), separate explanations are not given in this section.
13.1
Features
* Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * External clock or on-chip baud rate generator can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. Asynchronous mode * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RXD pin level directly in the case of a framing error
SCI0010A_000120030300
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Section 13 Serial Communication Interface 3 (SCI3)
Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors
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Section 13 Serial Communication Interface 3 (SCI3)
Table 13.1 Channel Configuration
Channel Channel 1*
1
Abbreviation SCI3
Pin SCK3 RXD TXD
Register SMR BRR SCR3 TDR SSR RDR RSR TSR
Register Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD H'F740 H'F741 H'F742 H'F743 H'F744 H'F745 H'F600 H'F601 H'F602 H'F603 H'F604 H'F605 H'F608
Channel 2
SCI3_2
SCK3_2 RXD_2 TXD_2
SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 RSR_2 TSR_2
Channel 3*
2
SCI3_3
SCK3_3* RXD_3 TXD_3
3
SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 RSR_3 TSR_3 SMCR
Notes: 1. The channel 1 of the SCI3 is used in on-board programming mode by boot mode. 2. The SCI3_3 function is incorporated in the H8/36024. 3. When this pin is used as the SCI3_3 function with the emulator used, the corresponding PCR value must be cleared to 0.
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Section 13 Serial Communication Interface 3 (SCI3)
SCK3
External clock
Internal clock (o/64, o/16, o/4, o) Baud rate generator
BRC Clock
BRR
Transmit/receive control circuit
SCR3 SSR
TXD
TSR
TDR
RXD
RSR
RDR Interrupt request (TEI, TXI, RXI, ERI)
Legend: Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR: Bit rate counter BRC:
Figure 13.1 Block Diagram of SCI3
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Internal data bus
SMR
Section 13 Serial Communication Interface 3 (SCI3)
13.2
Input/Output Pins
Table 13.2 shows the SCI3 pin configuration. Table 13.2 Pin Configuration
Pin Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbreviation SCK3 RXD TXD I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output
13.3
Register Descriptions
The SCI3 has the following registers for each channel. * * * * * * * * * Receive Shift Register (RSR) Receive Data Register (RDR) Transmit Shift Register (TSR) Transmit Data Register (TDR) Serial Mode Register (SMR) Serial Control Register 3 (SCR3) Serial Status Register (SSR) Bit Rate Register (BRR) SCI3_3 Module Control Register (SMCR)
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Section 13 Serial Communication Interface 3 (SCI3)
13.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 13.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one frame of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 13.3.3 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD pin. TSR cannot be directly accessed by the CPU. 13.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF.
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Section 13 Serial Communication Interface 3 (SCI3)
13.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI3's serial transfer format and select the baud rate generator clock source.
Bit 7 Bit Name COM Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 PM 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and PM bit settings are invalid in multiprocessor mode. In clocked synchronous mode, clear this bit to 0.
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Section 13 Serial Communication Interface 3 (SCI3)
Bit 1 0
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W R/W
Description Clock Select 0 and 1 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 13.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 13.3.8, Bit Rate Register (BRR)).
13.3.6
Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. For details on interrupt requests, refer to section 13.7, Interrupts.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 TE RE 0 0 R/W R/W Transmit Enable When this bit s set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled.
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Section 13 Serial Communication Interface 3 (SCI3)
Bit 3
Bit Name MPIE
Initial Value 0
R/W R/W
Description Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 13.6, Multiprocessor Communication Function.
2 1 0
TEIE CKE1 CKE0
0 0 0
R/W R/W R/W
Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. Clock Enable 0 and 1 Selects the clock source. * Asynchronous mode 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin. 11:Reserved * Clocked synchronous mode 00: On-chip clock (SCK3 pin functions as clock output) 01:Reserved 10: External clock (SCK3 pin functions as clock input) 11:Reserved
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Section 13 Serial Communication Interface 3 (SCI3)
13.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * * 6 RDRF 0 R/W When the TE bit in SCR3 is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR
[Clearing conditions]
Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When data is read from RDR
[Clearing conditions] * * 5 OER 0 R/W
Overrun Error [Setting condition] * * When an overrun error occurs in reception When 0 is written to OER after reading OER = 1 [Clearing condition]
4
FER
0
R/W
Framing Error [Setting condition] * * When a framing error occurs in reception When 0 is written to FER after reading FER = 1 [Clearing condition]
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Section 13 Serial Communication Interface 3 (SCI3)
Bit 3
Bit Name PER
Initial Value 0
R/W R/W
Description Parity Error [Setting condition] * * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition]
2
TEND
1
R
Transmit End [Setting conditions] * * When the TE bit in SCR3 is 0 When TDRE = 1 at transmission of the last bit of a 1frame serial transmit character When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR
[Clearing conditions] * * 1 MPBR 0 R
Multiprocessor Bit Receive MPBR stores the multiprocessor bit in the receive character data. When the RE bit in SCR3 is cleared to 0, its state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit character data.
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Section 13 Serial Communication Interface 3 (SCI3)
13.3.8
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 13.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 13.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 13.3 and 13.4 are values in active (highspeed) mode. Table 13.5 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 13.5 are values in active (high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode]
N=
x 106 - 1 64 x 22n-1 x B
x 106 - 1 x 100 (N + 1) x B x 64 x 22n-1
Error (%) =
[Clocked Synchronous Mode]
N=
8x 22n-1 xB x 106 - 1
[Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n: CSK1 and CSK0 settings in SMR (0 n 3)
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Section 13 Serial Communication Interface 3 (SCI3)
Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0.00 -18.62 n 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 n 1 1 0 0 0 0 0 0 0 0 0 2.4576 N 174 127 255 127 63 31 15 7 3 1 1 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 --
Operating Frequency (MHz) 3.6864 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73
Legend : A setting is available but error occurs
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Section 13 Serial Communication Interface 3 (SCI3)
Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 7.3728 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00
Operating Frequency (MHz) 8 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34
Legend : A setting is available but error occurs.
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Section 13 Serial Communication Interface 3 (SCI3)
Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency (MHz) 12.888 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16
Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.96 1.02 0.00 -2.34 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73
Legend --: A setting is available but error occurs.
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Section 13 Serial Communication Interface 3 (SCI3)
Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
(MHz) 2 Maximum Bit Rate (bit/s) 62500 n 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 20 Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 625000 n 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0
2.097152 65536 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 76800 93750 115200 125000 153600 156250 187500 192000 230400
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Section 13 Serial Communication Interface 3 (SCI3)
Table 13.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 2.5M 4M Legend Blank : No setting is available. -- : A setting is available but error occurs. * : Continuous transfer is not possible. 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- -- -- -- 1 1 0 0 0 0 0 0 -- -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- -- 0* 3 3 2 2 1 1 0 0 0 0 0 0 0 -- 0 249 124 249 99 199 99 159 79 39 15 7 3 1 -- 0* n 16 N
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Section 13 Serial Communication Interface 3 (SCI3)
Table 13.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 2.5M 4M 18 n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- -- -- N -- -- 140 69 112 224 112 179 89 44 17 8 4 -- -- -- n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- 0 -- 20 N -- -- 155 77 124 249 124 199 99 49 19 9 4 -- 1 --
Legend Blank : No setting is available. -- : A setting is available but error occurs. * : Continuous transfer is not possible.
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Section 13 Serial Communication Interface 3 (SCI3)
13.3.9
SCI3_3 Module Control Register (SMCR)
SMCR controls the SCI3_3 and module standby function.
Bit 7 to 4 3, 2 Bit Name Initial Value All 1 All 1 R/W Description Reserved These bits are always read as 1. Reserved These bits are always read as 1. When the emulator is used, these bits must be cleared to 0. 1 TXD_3 0 R/W TXD_3 Output Select Selects the function of the P57/TXD_3 pin. 0: General I/O port 1: TXD_3 output pin 0 MSTS3_3 0 R/W SCI3_3 Module Standby When this bit is set to 1, the SCI3_3 enters the standby state.
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Section 13 Serial Communication Interface 3 (SCI3)
13.4
Operation in Asynchronous Mode
Figure 13.2 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
LSB
Serial Start data bit
MSB Transmit/receive data
Parity bit
1
Stop bit
Mark state
1 bit
7 or 8 bits
1 bit, or none
1 or 2 bits
One unit of transfer data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication 13.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3's serial clock, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the clock frequency should be 16 times the bit rate used. When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.3.
Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (frame)
Figure 13.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 13 Serial Communication Interface 3 (SCI3)
13.4.2
SCI3 Initialization
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Start initialization Set the clock selection in SCR3. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clocked synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1. [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR3 to 1, and set RIE, TIE, TEIE, and MPIE bits. For transmit (TE=1), also set the TxD bit in PMR1. [4] Set the data transfer format in SMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR3 to 1. RE settings enable the RXD pin to be used. For transmission, set the TXD bit in PMR1 to 1 to enable the TXD output pin to be used. Also set the RIE, TIE, TEIE, and MPIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit.
Clear TE and RE bits in SCR3 to 0 [1] Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
[2]
Set value in BRR
[3]
Wait
[4]

Figure 13.4 Sample SCI3 Initialization Flowchart
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Section 13 Serial Communication Interface 3 (SCI3)
13.4.3
Data Transmission
Figure 13.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. The SCI3 checks the TDRE flag at the timing for sending the stop bit. 4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 6. Figure 13.6 shows a sample flowchart for transmission in asynchronous mode.
Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1
TDRE TEND LSI TXI interrupt operation request generated User processing
TDRE flag cleared to 0
Data written to TDR
TXI interrupt request generated
TEI interrupt request generated
Figure 13.5 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
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Section 13 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR
[2]
Yes
All data transmitted?
[1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [3] To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear TxD in PMR1 to 0, then clear the TE bit in SCR3 to 0.
No
Read TEND flag in SSR
No
TEND = 1
Yes
No
Break output?
[3]
Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0

Figure 13.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)
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Section 13 Serial Communication Interface 3 (SCI3)
13.4.4
Serial Data Reception
Figure 13.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed.
Start bit Serial data 1 0 D0 D1 1 frame Receive data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark state (idle state) 1
RDRF FER
LSI operation User processing
RXI request
RDRF cleared to 0 RDR data read
0 stop bit detected
ERI request in response to framing error
Framing error processing
Figure 13.7 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
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Section 13 Serial Communication Interface 3 (SCI3)
Table 13.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.8 shows a sample flow chart for serial data reception. Table 13.6 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
Note: * The RDRF flag retains the state it had before data reception.
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Section 13 Serial Communication Interface 3 (SCI3)
Start reception
Read OER, PER, and FER flags in SSR
[1]
Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR No RDRF = 1 Yes [2]
Read receive data in RDR
[1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RxD pin.
Yes All data received? (A) No Clear RE bit in SCR3 to 0 [3]
Figure 13.8 Sample Serial Reception Data Flowchart (Asynchronous Mode)(1)
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Section 13 Serial Communication Interface 3 (SCI3)
[4]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
No
PER = 1
Yes
Parity error processing
(A)
Clear OER, PER, and FER flags in SSR to 0

Figure 13.8 Sample Serial Reception Data Flowchart (Asynchronous Mode)(2)
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Section 13 Serial Communication Interface 3 (SCI3)
13.5
Operation in Clocked Synchronous Mode
Figure 13.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling fullduplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
8-bit One unit of transfer data (character or frame)
*
*
Synchronization clock
LSB MSB
Serial data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Note: * High except in continuous transfer
Don't care
Figure 13.9 Data Format in Clocked Synchronous Communication 13.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock, the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high.
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Section 13 Serial Communication Interface 3 (SCI3)
13.5.2
SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 13.4. 13.5.3 Serial Data Transmission
Figure 13.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. 3. 8-bit data is sent from the TXD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD pin. 4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 7. The SCK3 pin is fixed high at the end of transmission. Figure 13.11 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.
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Section 13 Serial Communication Interface 3 (SCI3)
Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6
Bit 7
1 frame
TDRE TEND LSI TXI interrupt operation request generated User processing
TDRE flag cleared to 0
1 frame
TXI interrupt request generated
TEI interrupt request generated
Data written to TDR
Figure 13.10 Example of SCI3 Transmission in Clocked Synchronous Mode
Start transmission
[1]
[1]
Read TDRE flag in SSR
No TDRE = 1 Yes
[2]
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Write transmit data to TDR
[2]
All data transmitted? No
Yes
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR3 to 0
Figure 13.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
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Section 13 Serial Communication Interface 3 (SCI3)
13.5.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 13.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. 2. 3. The SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. The SCI3 stores the receive data in RSR. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated.
4.
Serial clock Serial data
Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6
Bit 7
1 frame
RDRF OER LSI operation User processing
RXI interrupt request generated
1 frame
RDRF flag cleared to 0
RXI interrupt request generated
ERI interrupt request generated by overrun error Overrun error processing
RDR data read
RDR data has not been read (RDRF = 1)
Figure 13.12 Example of SCI3 Reception in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.13 shows a sample flow chart for serial data reception.
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Section 13 Serial Communication Interface 3 (SCI3)
Start reception
[1] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1.
Read OER flag in SSR
[1]
[2]
Yes
OER = 1
[4] No
Error processing (Continued below)
[3]
Read RDRF flag in SSR
[2]
[4]
No
RDRF = 1
Yes
Read receive data in RDR
Yes
All data received?
[3]
No
Clear RE bit in SCR3 to 0

[4]
Error processing
Overrun error processing
Clear OER flag in SSR to 0

Figure 13.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
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Section 13 Serial Communication Interface 3 (SCI3)
13.5.5
Simultaneous Serial Data Transmission and Reception
Figure 13.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
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Section 13 Serial Communication Interface 3 (SCI3)
Start transmission/reception
[1]
Read TDRE flag in SSR No
TDRE = 1
[1]
Yes
Write transmit data to TDR
Read OER flag in SSR
OER = 1
Yes
[4] Error processing
No
Read RDRF flag in SSR
[2]
No
RDRF = 1
Yes
Read receive data in RDR
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. [3] To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to 0. [4] If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 13.13.
Yes
All data received?
[3]
No
Clear TE and RE bits in SCR to 0

Figure 13.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)
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Section 13 Serial Communication Interface 3 (SCI3)
13.6
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 13.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER, to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 13 Serial Communication Interface 3 (SCI3)
Transmitting station
Serial transmission line
Receiving station A
(ID = 01)
Serial data
Receiving station B
(ID = 02)
H'01 (MPB = 1)
Receiving station C
(ID = 03)
H'AA
Receiving station D
(ID = 04)
(MPB = 0)
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID
Legend MPB: Multiprocessor bit
Figure 13.15 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 13.6.1 Multiprocessor Serial Data Transmission
Figure 13.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
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Section 13 Serial Communication Interface 3 (SCI3)
Start transmission
[1] Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To output a break in serial transmission, set the port PCR to 1, clear PDR to 0, then clear the TE bit in SCR3 to 0.
[1]
Read TDRE flag in SSR
No
TDRE = 1
[2]
Yes
Set MPBT bit in SSR
[3] Write transmit data to TDR
Yes
[2]
All data transmitted?
No
Read TEND flag in SSR
No
TEND = 1
Yes
No [3]
Break output?
Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0

Figure 13.16 Sample Multiprocessor Serial Transmission Flowchart
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Section 13 Serial Communication Interface 3 (SCI3)
13.6.2
Multiprocessor Serial Data Reception
Figure 13.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 13.18 shows an example of SCI3 operation for multiprocessor format reception.
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Section 13 Serial Communication Interface 3 (SCI3)
Start reception
[1] [2]
Set MPIE bit in SCR3 to 1
Read OER and FER flags in SSR
[1] [2]
[3]
Yes
FER+OER = 1
No
Read RDRF flag in SSR [3]
[4] [5]
No
RDRF = 1
Yes
Read receive data in RDR No
This station's ID?
Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again. When data is read from RDR, the RDRF flag is automatically cleared to 0. Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. If a receive error occurs, read the OER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value.
Yes
Read OER and FER flags in SSR Yes
FER+OER = 1
No
Read RDRF flag in SSR
No
RDRF = 1
[4]
[5] Error processing
Yes
Read receive data in RDR
(Continued on next page)
Yes
All data received?
No
[A]
Clear RE bit in SCR3 to 0

Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 13 Serial Communication Interface 3 (SCI3)
[5]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
[A]
Clear OER, and FER flags in SSR to 0

Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 13 Serial Communication Interface 3 (SCI3)
Start bit Serial data 1 0 D0
Receive data (ID1) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data1) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing RXI interrupt request MPIE cleared to 0 RDRF flag cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again ID1
RXI interrupt request is not generated, and RDR retains its state
(a) When data does not match this receiver's ID
Start bit Serial data 1 0 D0
Receive data (ID2) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data2) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing ID1 ID2 Data2
RXI interrupt request MPIE cleared to 0
RDRF flag cleared to 0 RDR data read
RXI interrupt request When data is this station's ID, reception is continued
RDRF flag cleared to 0 RDR data read MPIE set to 1 again
(b) When data matches this receiver's ID
Figure 13.18 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 13 Serial Communication Interface 3 (SCI3)
13.7
Interrupts
SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 13.7 shows the interrupt sources. Table 13.7 SCI3 Interrupt Requests
Interrupt Requests Receive Data Full Transmit Data Empty Transmission End Receive Error Abbreviation RXI TXI TEI ERI Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, and PER in SSR
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
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Section 13 Serial Communication Interface 3 (SCI3)
13.8
13.8.1
Usage Notes
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 13.8.2 Mark State and Break Sending
When TE is 0, the TXD pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TXD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TXD pin becomes an I/O port, and 1 is output from the TXD pin. To send a break during serial transmission, first set PCR to 1 and clear PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TXD pin becomes an I/O port, and 0 is output from the TXD pin. 13.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
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Section 13 Serial Communication Interface 3 (SCI3)
13.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 13.19. Thus, the reception margin in asynchronous mode is given by formula (1) below.
1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100(%) 2N N
... Formula (1)
[Legend\ N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula.
M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 13.19 Receive Data Sampling Timing in Asynchronous Mode
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Section 14 A/D Converter
Section 14 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The block diagram of the A/D converter is shown in figure 14.1.
14.1
* * * *
Features
* * *
*
10-bit resolution Four input channels Conversion time: at least 3.5 s per channel (at 20 MHz operation) Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16-bit data register for each channel Sample and hold function Two conversion start methods Software External trigger signal Interrupt request An A/D conversion end interrupt request (ADI) can be generated
ADCMS32A_000020020200
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Section 14 A/D Converter
Module data bus
Bus interface
Internal data bus
AVCC 10-bit D/A
Successive approximations register
A D D R A
A D D R B
A D D R C
A D D R D
A D C S R
A D C R
Analog multiplexer
+ Control circuit Comparator Sample-andhold circuit
o/4 o/8
AN0 AN1 AN2 AN3
ADI interrupt request
ADTRG Legend ADCR ADCSR ADDRA ADDRB ADDRC ADDRD
: : : : : :
A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Figure 14.1 Block Diagram of A/D Converter
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Section 14 A/D Converter
14.2
Input/Output Pins
Table 14.1 summarizes the input pins used by the A/D converter. Table 14.1 Pin Configuration
Pin Name Analog power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 A/D external trigger input pin Symbol AVCC AN0 AN1 AN2 AN3 ADTRG I/O Input Input Input Input Input Input External trigger input pin for starting A/D conversion Function Analog block power supply pin Analog input pins
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Section 14 A/D Converter
14.3
Register Description
The A/D converter has the following registers. * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) A/D Data Registers A to D (ADDRA to ADDRD)
14.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 14.2. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. Therefore byte access to ADDR should be done by reading the upper byte first then the lower one. Word access is also possible. ADDR is initialized to H'0000. Table 14.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel AN0 AN1 AN2 AN3 A/D Data Register to Be Stored Results of A/D Conversion ADDRA ADDRB ADDRC ADDRD
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Section 14 A/D Converter
14.3.2
A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit 7 Bit Name ADF Initial Value 0 R/W R/W Description A/D End Flag [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all the channels selected in scan mode When 0 is written after reading ADF = 1
[Clearing conditions] * 6 ADIE 0 R/W A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled by ADF when 1 is set 5 ADST 0 R/W A/D Start Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 CKS 0 R/W Clock Select Selects the A/D conversions time 0: Conversion time = 134 states (max.) 1: Conversion time = 70 states (max.) Clear the ADST bit to 0 before switching the conversion time.
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Section 14 A/D Converter
Bit 2 1 0
Bit Name CH2 CH1 CH0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Channel Select 0 to 2 Select analog input channels. When SCAN = 0 X00: AN0 X01: AN1 X10: AN2 X11: AN3 When SCAN = 1 X00: AN0 X01: AN0 to AN1 X10: AN0 to AN2 X11: AN0 to AN3
Legend X: Don't care.
14.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit 7 Bit Name TRGE Initial Value 0 R/W R/W Description Trigger Enable A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) when this bit is set to 1. The selection between the falling edge and rising edge of the external trigger pin (ADTRG) conforms to the WPEG5 bit in the interrupt edge select register 2 (IEGR2) 6 to 1 0 -- -- All 1 0 -- R/W Reserved These bits are always read as 1. Reserved Do not set this bit to 1, though the bit is readable/writable.
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Section 14 A/D Converter
14.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 14.4.1 Single Mode
In single mode, A/D conversion is performed once for the analog input on the specified single channel as follows: 1. 2. 3. 4. A/D conversion is started from the first channel when the ADST bit in ADCSR is set to 1, according to software or external trigger input. When A/D conversion is completed, the result is transferred to the corresponding A/D data register to the channel. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. Scan Mode
14.4.2
In scan mode, A/D conversion is performed sequentially for the analog input on the specified channels (four channels maximum) as follows: 1. When the ADST bit is set to 1 by software, or external trigger input, A/D conversion starts on the first channel in the group. 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first channel in the group starts again. 4. The ADST bit is not automatically cleared to 0. Steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
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Section 14 A/D Converter
14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 14.2 shows the A/D conversion timing. Table 14.3 shows the A/D conversion time. As indicated in figure 14.2, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 14.3. In scan mode, the values given in table 14.3 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states (fixed) when CKS = 1.
(1) o Address (2)
Write signal Input sampling timing
ADF tD tSPL tCONV Legend (1) : ADCSR write cycle (2) : ADCSR address : A/D conversion start delay tD tSPL : Input sampling time tCONV : A/D conversion time
Figure 14.2 A/D Conversion Timing
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Section 14 A/D Converter
Table 14.3 A/D Conversion Time (Single Mode)
CKS = 0 Item Symbol Min 6 -- 131 Typ -- 31 -- Max 9 -- 134 Min 4 -- 69 CKS = 1 Typ -- 15 -- Max 5 -- 70
A/D conversion start delay tD Input sampling time A/D conversion time tSPL tCONV
Note: All values represent the number of states.
14.4.4
External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit is set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 14.3 shows the timing.
o ADTRG
Internal trigger signal
ADST A/D conversion
Figure 14.3 External Trigger Input Timing
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Section 14 A/D Converter
14.5
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 14.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 14.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 14 A/D Converter
Digital output
111 110 101 100 011 010 001 000 1 8
Ideal A/D conversion characteristic
Quantization error
2 8
3 8
4 8
5 8
6 8
7 FS 8 Analog input voltage
Figure 14.4 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage
Offset error
Figure 14.5 A/D Conversion Accuracy Definitions (2)
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Section 14 A/D Converter
14.6
14.6.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 14.6). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 14.6.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board.
This LSI Sensor output impedance to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit
10 k 20 pF
Figure 14.6 Analog Input Circuit Example
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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits. This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. Even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operation. Thus, system stability can be improved. If the power supply voltage falls more, the reset state is automatically entered. If the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. Figure 15.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
15.1
Features
* Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. * Low-voltage detection circuit LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective specified values. Two pairs of detection levels for reset generation voltage are available: when only the LVDR circuit is used, or when the LVDI and LVDR circuits are both used.
LVI0000A_000020030300
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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
CK R
OVF PSS R
RES
Noise canceler
Q S Power-on reset circuit
Internal reset signal
Noise canceler
Vreset Vcc Ladder resistor Vint
+ - + - LVDINT LVDRES Interrupt control circuit LVDSR
Reference voltage generator
Interrupt request Low-voltage detection circuit
Legend PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: Prescaler S Low-voltage-detection control register Low-voltage-detection status register Low-voltage-detection reset signal Low-voltage-detection interrupt signal Reset detection voltage Power-supply fall/rise detection voltage
Figure 15.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
15.2
Register Descriptions
The low-voltage detection circuit has the following registers. * Low-voltage-detection control register (LVDCR) * Low-voltage-detection status register (LVDSR)
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Internal data bus
LVDCR
Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
15.2.1
Low-Voltage-Detection Control Register (LVDCR)
LVDCR is used to enable or disable the low-voltage detection circuit, set the detection levels for the LVDR function, enable or disable the LVDR function, and enable or disable generation of an interrupt when the power-supply voltage rises above or falls below the respective levels. Table 15.1 shows the relationship between the LVDCR settings and select functions. LVDCR should be set according to table 15.1.
Bit 7 Bit Name LVDE Initial Value 0* R/W R/W Description LVD Enable 0: The low-voltage detection circuit is not used (In standby mode) 1: The low-voltage detection circuit is used 6 to 4 3 LVDSEL All 1 0* R/W Reserved These bits are always read as 1, and cannot be modified. LVDR Detection Level Select 0: Reset detection voltage is 2.3 V (typ.) 1: Reset detection voltage is 3.6 V (typ.) When the falling or rising voltage detection interrupt is used, reset detection voltage of 2.3 V (typ.) should be used. When only a reset detection interrupt is used, reset detection voltage of 3.6 V (typ.) should be used. 2 LVDRE 0* R/W LVDR Enable 0: Disables the LVDR function 1: Enables the LVDR function 1 LVDDE 0 R/W Voltage-Fall-Interrupt Enable 0: Interrupt on the power-supply voltage falling below the selected detection level disabled 1: Interrupt on the power-supply voltage falling below the selected detection level enabled 0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising above the selected detection level disabled 1: Interrupt on the power-supply voltage rising above the selected detection level enabled Note: * Not initialized by LVDR but initialized by a power-on reset or WDT reset.
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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Table 15.1 LVDCR Settings and Select Functions
LVDCR Settings Select Functions
Low-VoltageDetection Falling Interrupt Low-VoltageDetection Rising Interrupt
LVDE
LVDSEL
LVDRE
LVDDE
LVDUE
Power-On Reset
LVDR
0 1 1 1 1 Legend
* 1 0 0 0
* 1 0 0 1 * means invalid.
* 0 1 1 1
* 0 0 1 1
O O O O O
O O
O O O
O O
15.2.2
Low-Voltage-Detection Status Register (LVDSR)
LVDSR indicates whether the power-supply voltage falls below or rises above the respective specified values.
Bit 7 to 2 1 Bit Name LVDDF Initial Value All 1 0* R/W R/W Description Reserved These bits are always read as 1, and cannot be modified. LVD Power-Supply Voltage Fall Flag [Setting condition] When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) [Clearing condition] Writing 0 to this bit after reading it as 1 0 LVDUF 0* R/W LVD Power-Supply Voltage Rise Flag [Setting condition] When the power supply voltage falls below Vint (D) while the LVDUE bit in LVDCR is set to 1, then rises above Vint (U) (typ. = 4.0 V) before falling below Vreset1 (typ. = 2.3 V) [Clearing condition] Writing 0 to this bit after reading it as 1 Note: * Initialized by LVDR.
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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
15.3
15.3.1
Operation
Power-On Reset Circuit
Figure 15.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 150 k). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin reaches the specified value, the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to release the internal reset signal after the prescaler S has counted 131,072 clock () cycles. The noise cancellation circuit of approximately 100 ns is incorporated to prevent the incorrect operation of the chip by noise on the RES pin. To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles within the specified time. The maximum time required for the power supply to rise and settle after power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) 90 x CRES (F) + 162/fOSC (MHz) (tPWON 3000 ms, CRES 0.22 F, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur.
tPWON Vcc
Vpor
Vss RES Vss PSS-reset signal OVF Internal reset signal
131,072 cycles PSS counter starts Reset released
Figure 15.2 Operational Timing of Power-On Reset Circuit
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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
15.3.2 (1)
Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detect) Circuit
Figure 15.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDRE bit in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur. When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state remains in place until a power-on reset is generated. When the power-supply voltage rises above the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock () cycles, and then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in LVDCR are not initialized. Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that point, the low-voltage detection reset may not occur. If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
VCC
Vreset
VLVDRmin VSS LVDRES
PSS-reset signal
OVF
Internal reset signal
131,072 cycles PSS counter starts
Reset released
Figure 15.3 Operational Timing of LVDR Circuit
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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
(2)
LVDI (Interrupt by Low Voltage Detect) Circuit
Figure 15.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits because incorrect operation may occur. When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time, an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be saved in the external EEPROM, etc, and a transition must be made to standby mode or subsleep mode. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed.
Vcc
Vint (U) Vint (D)
Vreset1 VSS
LVDINT
LVDDE
LVDDF
LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated
Figure 15.4 Operational Timing of LVDI Circuit
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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
(3)
Procedures for Clearing Settings when Using LVDR and LVDI
To operate or release the low-voltage detection circuit normally, follow the procedure described below. Figure 15.5 shows the timing for the operation and release of the low-voltage detection circuit. 1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1. 2. Wait for 50 s (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc. Then, clear the LVDDF and LVDUF bits in LVDSR to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, as required. 3. To release the low-voltage detection circuit, start by clearing all of the LVDRE, LVDDE, and LVDUE bits to 0. Then clear the LVDE bit to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.
LVDE
LVDRE
LVDDE
LVDUE
tLVDON
Figure 15.5 Timing for Operation/Release of Low-Voltage Detection Circuit
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Section 16 Power Supply Circuit
Section 16 Power Supply Circuit
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the internal voltage will be practically the same as the external voltage. It is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit.
16.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1 F between VCL and VSS, as shown in figure 16.1. The internal step-down circuit is made effective simply by adding this external circuit. In the external circuit interface, the external power supply voltage connected to VCC and the GND potential connected to VSS are the reference levels. For example, for port input/output levels, the VCC level is the reference for the high level, and the VSS level is that for the low level. The A/D converter analog power supply is not affected by the internal step-down circuit.
VCC VCC = 3.0 to 5.5 V
Step-down circuit
VCL
Internal logic
Internal power supply
Stabilization capacitance (approx. 0.1 F)
VSS
Figure 16.1 Power Supply Connection when Internal Step-Down Circuit is Used
PSCKT00A_000020020200
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Section 16 Power Supply Circuit
16.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 16.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
VCC VCC = 3.0 to 3.6 V
Step-down circuit
VCL
Internal logic
Internal power supply
VSS
Figure 16.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
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Section 17 List of Registers
Section 17 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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Section 17 List of Registers
17.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Register Name Serial mode register_3 Bit rate register_3 Serial control register 3_3 Transmit data register_3 Serial status register_3 Receive data register_3 SCI3_3 module control register Low-voltage-detection control register Low-voltage-detection status register Serial mode register_2 Bit rate register_2 Serial control register 3_2 Transmit data register_2 Serial status register_2 Receive data register_2 Timer mode register W Timer control register W Abbreviation SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 SMCR LVDCR LVDSR SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 TMRW TCRW Bit No Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 H'F600 H'F601 H'F602 H'F603 H'F604 H'F605 H'F606, H'F607 H'F608 H'F730 H'F731 H'F740 H'F741 H'F742 H'F743 H'F744 H'F745 H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 Module Name SCI3_3 SCI3_3 SCI3_3 SCI3_3 SCI3_3 SCI3_3 SCI3_3 SCI3_3 LVDC*
1
Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16* 16*
2 2
3 3 3 3 3 3 3 2 2 3 3 3 3 3 3 2 2 2 2 2 2 2 2
LVDC*1 SCI3_2 SCI3_2 SCI3_2 SCI3_2 SCI3_2 SCI3_2 Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W
Timer interrupt enable register W TIERW Timer status register W Timer I/O control register 0 Timer I/O control register 1 Timer counter General register A TSRW TIOR0 TIOR1 TCNT GRA
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Section 17 List of Registers
Register Name General register B General register C General register D Flash memory control register 1 Flash memory control register 2 Erase block register 1 Flash memory enable register Timer control register V0 Timer control/status register V Timer constant register A Timer constant register B Timer counter V Timer control register V1 Serial mode register Bit rate register Serial control register 3 Transmit data register Serial status register Receive data register A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register Timer control/status register WD Timer counter WD
Abbreviation GRB GRC GRD FLMCR1 FLMCR2 EBR1 FENR TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 SMR BRR SCR3 TDR SSR RDR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR TCSRWD TCWD
Bit No Address 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 H'FF8A H'FF8C H'FF8E H'FF90 H'FF91 H'FF93 H'FF9B H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD H'FFB0 H'FFB2 H'FFB4 H'FFB6 H'FFB8 H'FFB9 H'FFC0 H'FFC1
Module Name Timer W Timer W Timer W ROM ROM ROM ROM Timer V Timer V Timer V Timer V Timer V Timer V SCI3 SCI3 SCI3 SCI3 SCI3 SCI3
Data Bus Access Width State 16*2 16*2 16* 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
2
2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2
A/D 8 converter A/D 8 converter A/D 8 converter A/D 8 converter A/D 8 converter A/D 8 converter WDT* WDT*
3
8 8
3
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Section 17 List of Registers
Register Name Timer mode register WD Address break control register Address break status register Break address register H Break address register L Break data register H Break data register L Port pull-up control register 1 Port pull-up control register 5 Port data register 1 Port data register 2 Port data register 5 Port data register 7 Port data register 8 Port data register B Port mode register 1 Port mode register 5 Port control register 1 Port control register 2 Port control register 5 Port control register 7 Port control register 8 System control register 1 System control register 2 Interrupt edge select register 1
Abbreviation TMWD ABRKCR ABRKSR BARH BARL BDRH BDRL PUCR1 PUCR5 PDR1 PDR2 PDR5 PDR7 PDR8 PDRB PMR1 PMR5 PCR1 PCR2 PCR5 PCR7 PCR8 SYSCR1 SYSCR2 IEGR1
Bit No Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFC2 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFD0 H'FFD1 H'FFD4 H'FFD5 H'FFD8 H'FFDA H'FFDB H'FFDD H'FFE0 H'FFE1 H'FFE4 H'FFE5 H'FFE8 H'FFEA H'FFEB H'FFF0 H'FFF1 H'FFF2
Module Name WDT*3 Address break Address break Address break Address break Address break Address break I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Powerdown Powerdown
Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Interrupts 8
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Section 17 List of Registers
Register Name Interrupt edge select register 2 Interrupt enable register 1 Interrupt flag register 1 Wake-up interrupt flag register
Abbreviation IEGR2 IENR1 IRR1 IWPR
Bit No Address 8 8 8 8 8 8 H'FFF3 H'FFF4 H'FFF6 H'FFF8 H'FFF9 H'FFFA
Module Name
Data Bus Access Width State 2 2 2 2 2 2
Interrupts 8 Interrupts 8 Interrupts 8 Interrupts 8 Powerdown Powerdown 8 8
Module standby control register 1 MSTCR1 Module standby control register 2 MSTCR2
Notes: 1. LVDC: Low-voltage detection circuits (optional) 2. Only word access can be used. 3. WDT: Watchdog timer
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Section 17 List of Registers
17.2
Register Bits
Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Register Name SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 SMCR LVDCR LVDSR SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT Bit 7 COM BRR7 TIE TDR7 TDRE RDR7 - LVDE - COM BRR7 TIE TDR7 TDRE RDR7 CTS CCLR OVIE OVF -- -- Bit 6 CHR BRR6 RIE TDR6 RDRF RDR6 - - - CHR BRR6 RIE TDR6 RDRF RDR6 -- CKS2 -- -- IOB2 IOD2 Bit 5 PE BRR5 TE TDR5 OER RDR5 - - - PE BRR5 TE TDR5 OER RDR5 BUFEB CKS1 -- -- IOB1 IOD1 Bit 4 PM BRR4 RE TDR4 FER RDR4 - - - PM BRR4 RE TDR4 FER RDR4 BUFEA CKS0 -- -- IOB0 IOD0 Bit 3 STOP BRR3 MPIE TDR3 PER RDR3 - Bit 2 MP BRR2 TEIE TDR2 TEND RDR2 - Bit 1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 TXD_3 LVDDE LVDDF CKS1 BRR1 CKE1 TDR1 MPBR RDR1 PWMC TOB IMIEB IMFB IOA1 IOC1 Bit 0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 MSTS3_3 LVDUE LVDUF CKS0 BRR0 CKE0 TDR0 MPBT RDR0 PWMB TOA IMIEA IMFA IOA0 IOC0 TCNT8 TCNT0 GRA8 GRA0 GRB8 GRB0 Timer W LVDC (optional) SCI3_2 Module Name SCI3_3
LVDSEL LVDRE - STOP BRR3 MPIE TDR3 PER RDR3 -- TOD IMIED IMFD -- -- - MP BRR2 TEIE TDR2 TEND RDR2 PWMD TOC IMIEC IMFC IOA2 IOC2
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT7 TCNT6 GRA14 GRA6 GRB14 GRB6 TCNT5 GRA13 GRA5 GRB13 GRB5 TCNT4 GRA12 GRA4 GRB12 GRB4 TCNT3 GRA11 GRA3 GRB11 GRB3 TCNT2 GRA10 GRA2 GRB10 GRB2 TCNT1 GRA9 GRA1 GRB9 GRB1
GRA
GRA15 GRA7
GRB
GRB15 GRB7
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Section 17 List of Registers Register Name GRC Module Name Timer W
Bit 7 GRC15 GRC7
Bit 6 GRC14 GRC6 GRD14 GRD6 SWE -- -- -- CMIEA CMFA
Bit 5 GRC13 GRC5 GRD13 GRD5 ESU -- -- -- OVIE OVF
Bit 4 GRC12 GRC4 GRD12 GRD4 PSU -- EB4 -- CCLR1 --
Bit 3 GRC11 GRC3 GRD11 GRD3 EV -- EB3 -- CCLR0 OS3
Bit 2 GRC10 GRC2 GRD10 GRD2 PV -- EB2 -- CKS2 OS2
Bit 1 GRC9 GRC1 GRD9 GRD1 E -- EB1 -- CKS1 OS1
Bit 0 GRC8 GRC0 GRD8 GRD0 P -- EB0 -- CKS0 OS0
GRD
GRD15 GRD7
FLMCR1 FLMCR2 EBR1 FENR TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 SMR BRR SCR3 TDR SSR RDR ADDRA
-- FLER -- FLSHE CMIEB CMFB
ROM
Timer V
TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0 TCNTV7 TCNTV6 TCNTV5 TCNTV4 -- COM BRR7 TIE TDR7 TDRE RDR7 AD9 AD1 -- CHR BRR6 RIE TDR6 RDRF RDR6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- TCWE TCWD6 -- -- PE BRR5 TE TDR5 OER RDR5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- B4WI TCWD5 -- TVEG1 PM BRR4 RE TDR4 FER RDR4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- TCNTV3 TCNTV2 TCNTV1 TCNTV0 TVEG0 STOP BRR3 MPIE TDR3 PER RDR3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- TRGE MP BRR2 TEIE TDR2 TEND RDR2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- WDON TCWD2 CKS2 -- CKS1 BRR1 CKE1 TDR1 MPBR RDR1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- B0WI TCWD1 CKS1 ICKS0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- WRST TCWD0 CKS0 WDT* A/D converter SCI3
ADDRB
AD9 AD1
ADDRC
AD9 AD1
ADDRD
AD9 AD1
ADCSR ADCR
ADF TRGE
TCSRWD B6WI TCWD TMWD TCWD7 --
TCSRWE B2WI TCWD4 -- TCWD3 CKS3
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Section 17 List of Registers Register Name ABRKCR ABRKSR BARH BARL BDRH BDRL PUCR1 PUCR5 PDR1 PDR2 PDR5 PDR7 PDR8 PDRB PMR1 PMR5 PCR1 PCR2 PCR5 PCR7 PCR8 SYSCR1 SYSCR2 IEGR1 IEGR2 IENR1 IRR1 IWPR MSTCR1 MSTCR2 Module Name Address break
Bit 7 RTINTE ABIF BARH7 BARL7 BDRH7 BDRL7 PUCR17 -- P17 -- P57 -- -- -- IRQ3 POF57 PCR17 -- PCR57 -- -- SSBY SMSEL -- -- IENDT IRRDT -- --
Bit 6 CSEL1 ABIE BARH6 BARL6 BDRH6 BDRL6
Bit 5 CSEL0 -- BARH5 BARL5 BDRH5 BDRL5
Bit 4 ACMP2 -- BARH4 BARL4 BDRH4 BDRL4
Bit 3 ACMP1 -- BARH3 BARL3 BDRH3 BDRL3
Bit 2 ACMP0 -- BARH2 BARL2 BDRH2 BDRL2
Bit 1 DCMP1 -- BARH1 BARL1 BDRH1 BDRL1
Bit 0 DCMP0 -- BARH0 BARL0 BDRH0 BDRL0
PUCR16 PUCR15 PUCR14 -- -- P16 -- P56 P76 -- -- -- POF56 PCR16 -- PCR56 PCR76 -- STS2 -- -- -- -- -- -- --
PUCR12 PUCR11 PUCR10 I/O port
PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 P15 -- P55 P75 -- -- -- WKP5 PCR15 -- PCR55 PCR75 -- STS1 DTON -- WPEG5 IENWP -- IWPF5 MSTS3 -- P14 -- P54 P74 P84 -- IRQ0 WKP4 PCR14 -- PCR54 PCR74 PCR84 STS0 MA2 -- WPEG4 -- -- IWPF4 MSTAD -- -- -- P53 P73 P83 PB3 TXD2 WKP3 -- -- PCR53 PCR73 PCR83 -- MA1 IEG3 WPEG3 IEN3 IRRI3 IWPF3 P12 P22 P52 P72 P82 PB2 -- WKP2 PCR12 PCR22 PCR52 PCR72 PCR82 -- MA0 -- WPEG2 -- -- IWPF2 P11 P21 P51 P71 P81 PB1 TXD WKP1 PCR11 PCR21 PCR51 PCR71 PCR81 -- -- -- WPEG1 -- -- IWPF1 MSTTV -- P10 P20 P50 P70 P80 PB0 -- WKP0 PCR10 PCR20 PCR50 PCR70 PCR80 -- -- IEG0 WPEG0 IEN0 IRRI0 IWPF0 -- -- Power-down Interrupts Power-down
MSTWD MSTTW -- --
MSTS3_2 --
Note:
*
WDT: Watchdog timer
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Section 17 List of Registers
17.3
Register Name SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 SMCR LVDCR LVDSR SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT GRA GRB GRC GRD FLMCR1 FLMCR2 EBR1 FENR
Register States in Each Operating Mode
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Subsleep Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- Initialized -- Initialized -- Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- Initialized -- Initialized -- ROM Timer W SCI3_2 LVDC (optional) Module SCI3_3
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Section 17 List of Registers Register Name TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 SMR BRR SCR3 TDR SSR RDR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Subsleep Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Module Timer V
SCI3
A/D converter
TCSRWD Initialized TCWD TMWD ABRKCR ABRKSR BARH BARL BDRH BDRL PUCR1 PUCR5 PDR1 PDR2 PDR5 PDR7 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
WDT*
Address Break
I/O port
Rev. 4.00 Sep. 23, 2005 Page 248 of 354 REJ09B0025-0400
Section 17 List of Registers Register Name PDR8 PDRB PMR1 PMR5 PCR1 PCR2 PCR5 PCR7 PCR8 SYSCR1 SYSCR2 IEGR1 IEGR2 IENR1 IRR1 IWPR MSTCR1 MSTCR2
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Subsleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Module I/O port
Power-down
Interrupts
Power-down
Note:
is not initialized * WDT: Watchdog timer
Rev. 4.00 Sep. 23, 2005 Page 249 of 354 REJ09B0025-0400
Section 17 List of Registers
Rev. 4.00 Sep. 23, 2005 Page 250 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
Section 18 Electrical Characteristics
18.1 Absolute Maximum Ratings
Table 18.1 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Ports other than Port B Port B Operating temperature Storage temperature Note: * Topr Tstg Symbol VCC AVCC VIN Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 -55 to +125 Unit V V V V C C Note *
Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability.
18.2
18.2.1 (1)
Electrical Characteristics (F-ZTATTM Version)
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
oOSC (MHz) 20.0 10.0
2.0
3.0
4.0
5.5
VCC (V)
* AVCC = 3.3 V to 5.5 V * Active mode * Sleep mode
Rev. 4.00 Sep. 23, 2005 Page 251 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
(2)
Power Supply Voltage and Operating Frequency Range
o (MHz)
20.0 10.0
1.0 3.0 4.0 5.5 VCC (V)
* AVCC = 3.3 V to 5.5 V * Active mode * Sleep mode (When MA2 = 0 in SYSCR2) o (kHz)
3125 1250
78.125 3.0 4.0 5.5 VCC (V)
* AVCC = 3.3 V to 5.5 V * Active mode * Sleep mode (When MA2 = 1 in SYSCR2)
(3)
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
o (MHz)
20.0 10.0
2.0 3.3 4.0 5.5 AVCC (V)
* VCC = 3.0 V to 5.5 V * Active mode * Sleep mode
Rev. 4.00 Sep. 23, 2005 Page 252 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
(4)
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used
osc (MHz) 20.0 16.0
2.0 Vcc(V) 3.0 4.5 5.5
Operation guarantee range Operation guarantee range except A/D conversion accuracy
Rev. 4.00 Sep. 23, 2005 Page 253 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.2.2
DC Characteristics
Table 18.2 DC Characteristics (1) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated.
Values Item Symbol Applicable Pins Test Condition Min VCC x 0.8 Typ Max -- VCC + 0.3 Unit V Notes RES, NMI VCC = 4.0 V to 5.5 V WKP0 to WKP5, IRQ0, IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, SCK3_2, 1 SCK3_3* , TRGV RXD, RXD_2, 1 RXD_3* , P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70, P84 to P80 PB3 to PB0 VCC = 4.0 V to 5.5 V
Input high VIH voltage
VCC x 0.9
--
VCC + 0.3
VCC x 0.7
--
VCC + 0.3
V
VCC x 0.8
--
VCC + 0.3
VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V
VCC x 0.7 VCC x 0.8 VCC - 0.5 VCC - 0.3 -0.3
-- -- -- -- --
AVCC + 0.3 V AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.2 V V
OSC1
Input low voltage
VIL
RES, NMI VCC = 4.0 V to 5.5 V WKP0 to WKP5, IRQ0, IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, SCK3_2, 1 SCK3_3* , TRGV RXD, RXD_2, 1 RXD_3* , P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70, P84 to P80 PB3 to PB0 OSC1 VCC = 4.0 V to 5.5 V
-0.3
--
VCC x 0.1
-0.3
--
VCC x 0.3
V
-0.3
--
VCC x 0.2
VCC = 4.0 V to 5.5 V
-0.3 -0.3
-- --
0.5 0.3
V
Rev. 4.00 Sep. 23, 2005 Page 254 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Item Output high voltage Symbol VOH Applicable Pins P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70, P84 to P80 P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70 P84 to P80 Test Condition VCC = 4.0 V to 5.5 V -IOH = 1.5 mA -IOH = 0.1 mA VCC - 0.5 -- -- Min Typ Max -- Unit V Notes
VCC - 1.0 --
Output low voltage
VOL
VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA VCC = 4.0 V to 5.5 V IOL = 20.0 mA VCC = 4.0 V to 5.5 V IOL = 10.0 mA VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA
--
--
0.6
V
-- --
-- --
0.4 1.5 V
--
--
1.0
--
--
0.4
-- --
-- --
0.4 1.0 A
Input/ output leakage current
| IIL |
OSC1, RES, NMI VIN = 0.5 V to WKP0, WKP5, (VCC - 0.5 V) IRQ0, IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, 1 RXD_2, RXD_3* , SCK3, SCK3_2, 1 SCK3_3* P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70, P84 to P80 PB3 to PB0 VIN = 0.5 V to (VCC - 0.5 V)
--
--
1.0
A
VIN = 0.5 V to (AVCC - 0.5 V) VCC = 5.0 V, VIN = 0.0 V VCC = 3.0 V, VIN = 0.0 V
-- 50.0 --
-- -- 60.0
1.0 300.0 --
A A Reference value
Pull-up MOS current
-Ip
P12 to P10, P17 to P14, P55 to P50
Rev. 4.00 Sep. 23, 2005 Page 255 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Item Input capacitance Symbol Cin Applicable Pins All input pins except power supply pins VCC Test Condition f = 1 MHz, VIN = 0.0 V, Ta = 25C Active mode 1 VCC = 5.0 V, fOSC = 20 MHz Active mode 1 VCC = 3.0 V, fOSC = 10 MHz VCC Active mode 2 VCC = 5.0 V, fOSC = 20 MHz Active mode 2 VCC = 3.0 V, fOSC = 10 MHz Sleep ISLEEP1 mode current consumption VCC Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz VCC Sleep mode 2 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 2 VCC = 3.0 V, fOSC = 10 MHz ISTBY Standby mode current consumption VCC Min -- Typ -- Max 15.0 Unit pF Notes
Active IOPE1 mode current consumption
--
15.0
30.0
mA
*
2
--
8.0
--
* Reference value mA *
2
2
IOPE2
--
1.8
3.0
--
1.2
--
* Reference value mA *
2
2
--
11.5
22.5
--
6.5
--
* Reference value mA *
2
2
ISLEEP2
--
1.7
2.7
--
1.1
--
* Reference value A *
2
2
--
--
5.0
Rev. 4.00 Sep. 23, 2005 Page 256 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Item Symbol Applicable Pins VCC Test Condition Min 2.0 Typ -- Max -- Unit V Notes
RAM data VRAM retaining voltage
Notes: 1. The SCK3_3 and RXD_3 pins are not available in the H8/36014. 2. Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Mode Active mode 1 Active mode 2 Sleep mode 1 Sleep mode 2 Standby mode VCC VCC RES Pin VCC Internal State Operates Operates (OSC/64) Only timers operate Only timers operate (OSC/64) CPU and timers both stop VCC Main clock: ceramic or crystal resonator VCC Other Pins VCC Oscillator Pins Main clock: ceramic or crystal resonator
Rev. 4.00 Sep. 23, 2005 Page 257 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
Table 18.2 DC Characteristics (2) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise indicated.
Applicable Item Allowable output low current (per pin) Symbol IOL Pins Output pins except port 8 Port 8 Port 8 Output pins except port 8 Allowable output low current (total) IOL Output pins except port 8 Port 8 Output pins except port 8 Port 8 Allowable output high I -IOH I current (per pin) All output pins VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Test Condition Min VCC = 4.0 V to 5.5 V -- -- -- -- -- -- -- -- -- -- Allowable output high I -IOH I current (total) All output pins VCC = 4.0 V to 5.5 V -- -- Values Typ -- -- -- -- -- -- -- -- -- -- -- -- Max 2.0 20.0 10.0 0.5 40.0 80.0 20.0 40.0 2.0 0.2 30.0 8.0 Unit mA mA mA mA mA mA mA mA mA mA mA mA
Rev. 4.00 Sep. 23, 2005 Page 258 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.2.3
AC Characteristics
Table 18.3 AC Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins OSC1, OSC2 Values Test Condition Min Typ -- -- -- -- -- -- Max 20.0 10.0 64 12.8 -- 10.0 Unit MHz MHz tOSC s tcyc ms *
2
Item System clock oscillation frequency System clock () cycle time Instruction cycle time Oscillation stabilization time (crystal resonator)
Symbol fOSC
Reference Figure *
1
VCC = 4.0 V to 5.5 V 2.0 2.0
tcyc
1 -- 2
trc
OSC1, OSC2 OSC1, OSC2 OSC1
--
trc Oscillation stabilization time (ceramic resonator) External clock high width External clock low width External clock rise time External clock fall time tCPH tCPL tCPr tCPf
--
--
5.0
ms
VCC = 4.0 V to 5.5 V 20.0 40.0 VCC = 4.0 V to 5.5 V 20.0 40.0 VCC = 4.0 V to 5.5 V -- -- VCC = 4.0 V to 5.5 V -- --
-- -- -- -- -- -- -- --
-- -- -- -- 10.0 15.0 10.0 15.0
ns ns ns ns ns ns ns ns
Figure 18.1
OSC1
OSC1
OSC1
Rev. 4.00 Sep. 23, 2005 Page 259 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Test Condition Min Typ -- Max -- Unit ms
Item RES pin low width
Symbol tREL
Applicable Pins RES
Reference Figure Figure 18.2
At power-on and in trc modes other than those below In active mode and 200 sleep mode operation
--
--
ns
Input pin high width
tIH
NMI, IRQ0, IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD NMI, IRQ0, IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD
2
--
--
tcyc
Figure 18.3
Input pin low width
tIL
2
--
--
tcyc
Notes: 1. When an external clock is input, the minimum system clock oscillator frequency is 1.0 MHz. 2. Determined by MA2 to MA0 in system control register 2 (SYSCR2).
Rev. 4.00 Sep. 23, 2005 Page 260 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
Table 18.4 Serial Interface (SCI3) Timing VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins SCK3, SCK3_2, SCK3_3* Values Test Condition Min 4 6 Typ Max Unit -- -- -- -- tcyc tcyc Reference Figure Figure 18.4
Item Input clock cycle Asynchronous Clocked synchronous
Symbol tScyc
Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous)
tSCKW
SCK3, SCK3_2, SCK3_3* TXD, TXD_2, TXD_3* RXD, RXD_2, RXD_3* RXD, RXD_2, RXD_3* VCC = 4.0 V to 5.5 V
0.4
--
0.6
tScyc
tTXD
-- --
-- -- -- -- -- --
1 1 -- -- -- --
tcyc tcyc ns ns ns ns
Figure 18.5
tRXS
VCC = 4.0 V to 5.5 V
50.0 100.0
tRXH
VCC = 4.0 V to 5.5 V
50.0 100.0
Note:
*
The SCK3_3, RXD_3, and TXD_3 pins are not available in the H8/36014.
Rev. 4.00 Sep. 23, 2005 Page 261 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.2.4
A/D Converter Characteristics
Table 18.5 A/D Converter Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins AVCC AN3 to AN0 AVCC Test Condition Values Min 3.3 VSS - 0.3 AVCC = 5.0 V -- fOSC = 20 MHz AVCC -- 50 -- A * Reference value *
3 2
Item
Symbol
Typ Max VCC -- -- 5.5
Unit V
Notes *
1
Analog power supply AVCC voltage Analog input voltage AVIN Analog power supply AIOPE current
AVCC + 0.3 V 2.0 mA
AISTOP1
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy CAIN RAIN
AVCC AN3 to AN0 AN3 to AN0
-- -- -- 10 AVCC = 3.3 V 134 to 5.5 V -- -- -- -- -- AVCC = 4.0 V 70 to 5.5 V -- -- -- -- --
-- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- --
5.0 30.0 5.0 10 -- 7.5 7.5 7.5 0.5 8.0 -- 7.5 7.5 7.5 0.5 8.0
A pF k bit tcyc LSB LSB LSB LSB LSB tcyc LSB LSB LSB LSB LSB
Rev. 4.00 Sep. 23, 2005 Page 262 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Min Typ Max -- -- -- -- -- -- -- 3.5 3.5 3.5 0.5 4.0 Unit tcyc LSB LSB LSB LSB LSB Notes
Item Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
Symbol
Applicable Pins
Test Condition
AVCC = 4.0 V 134 to 5.5 V -- -- -- -- --
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby and subsleep modes while the A/D converter is idle.
18.2.5
Watchdog Timer Characteristics
Table 18.6 Watchdog Timer Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins Test Condition Values Min 0.2 Typ 0.4 Max -- Unit s Notes *
Item On-chip oscillator overflow time Note: *
Symbol tOVF
Shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
Rev. 4.00 Sep. 23, 2005 Page 263 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.2.6
Flash Memory Characteristics
Table 18.7 Flash Memory Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Test Condition Values Min -- -- 1000 1 50 1n6 7 n 1000 Additionalprogramming 28 198 8 5 5 4 2 2 100 -- Typ 7 100 10000 -- -- 30 200 10 -- -- -- -- -- -- -- Max 200 1200 -- -- -- 32 202 12 -- -- -- -- -- -- 1000 Unit ms ms Times s s s s s s s s s s s Times
Item Programming time (per 128 bytes)* * * Erase time (per block) * * * Reprogramming count Programming Wait time after SWE 1 bit setting* Wait time after PSU 1 bit setting* Wait time after P bit setting **
14 136 124
Symbol tP tE NWEC x y z1 z2 z3 Wait time after P bit clear* Wait time after PSU 1 bit clear* Wait time after PV 1 bit setting* Wait time after 1 dummy write* Wait time after PV bit clear* Wait time after SWE 1 bit clear* Maximum 145 programming count* * *
1 1
N
Rev. 4.00 Sep. 23, 2005 Page 264 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Min 1 100 10 10 10 20 2 4 100 -- Typ -- -- -- -- -- -- -- -- -- -- Max -- -- 100 -- -- -- -- -- -- 120 Unit s s ms s s s s s s Times
Item Erase Wait time after SWE 1 bit setting* Wait time after ESU 1 bit setting* Wait time after E bit 16 setting* * Wait time after E bit clear* Wait time after ESU 1 bit clear* Wait time after EV 1 bit setting* Wait time after 1 dummy write* Wait time after EV bit clear* Wait time after SWE 1 bit clear* Maximum erase count* * *
167 1 1
Symbol x y z N
Test Condition
Notes: 1. Make the time settings in accordance with the program/erase algorithms. 2. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) 3. The time required to erase one block. (Indicates the time for which the E bit in flash memory control register 1 (FLMCR1) is set. The erase-verify time is not included.) 4. Programming time maximum value (tP (max.)) = wait time after P bit setting (z) x maximum programming count (N) 5. Set the maximum programming count (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (tP (max.)). The wait time after P bit setting (z1, z2) should be changed as follows according to the value of the programming count (n). Programming count (n) 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Erase time maximum value (tE (max.)) = wait time after E bit setting (z) x maximum erase count (N) 7. Set the maximum erase count (N) according to the actual set value of (z), so that it does not exceed the erase time maximum value (tE (max.)).
Rev. 4.00 Sep. 23, 2005 Page 265 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.2.7
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 18.8 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition LVDSEL = 0 LVDSEL = 0 LVDSEL = 0 LVDSEL = 1 Values Min 3.3 -- -- 3.0 1.0 50 LVDE = 1, Vcc = 5.0 V, When a 32kHz crystal resonator is not used Typ 3.7 4.0 2.3 3.6 -- -- -- Max -- 4.5 2.7 4.2 -- -- 350 Unit V V V V V s A
Item
Symbol Vint (D) Vint (U) Vreset1 Vreset2 VLVDRmin tLVDON ISTBY
Power-supply falling detection voltage Power-supply rising detection voltage Reset detection voltage 1*1 Reset detection voltage 2*
2
Lower-limit voltage of LVDR 3 operation* LVD stabilization time Current consumption in standby mode
Notes: 1. This voltage should be used when the falling and rising voltage detection function is used. 2. Select the low-voltage reset 2 when only the low-voltage detection reset is used. 3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset may not occur. Therefore sufficient evaluation is required.
Rev. 4.00 Sep. 23, 2005 Page 266 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.2.8
Power-On Reset Circuit Characteristics (Optional)
Table 18.9 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min 100 -- Typ 150 -- Max -- 100 Unit k mV
Item Pull-up resistance of RES pin Power-on reset start voltage* Note: *
Symbol RRES Vpor
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely. In order to remove charge of the RES pin, it is recommended that the diode be placed in the Vcc side. If the power-supply voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
18.3
18.3.1 (1)
Electrical Characteristics (Masked ROM Version)
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
oOSC (MHz) 20.0 10.0
2.0
2.7
4.0
5.5
VCC (V)
* AVCC = 3.0 V to 5.5 V * Active mode * Sleep mode
Rev. 4.00 Sep. 23, 2005 Page 267 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
(2)
Power Supply Voltage and Operating Frequency Range
o (MHz)
20.0 10.0
1.0 2.7 4.0 5.5 VCC (V)
* AVCC = 3.0 V to 5.5 V * Active mode * Sleep mode (When MA2 = 0 in SYSCR2) o (kHz)
3125 1250
78.125 2.7 4.0 5.5 VCC (V)
* AVCC = 3.0 V to 5.5 V * Active mode * Sleep mode (When MA2 = 1 in SYSCR2)
Rev. 4.00 Sep. 23, 2005 Page 268 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
(3)
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
o (MHz)
20.0 10.0
2.0 3.0 4.0 5.5 AVCC (V)
* VCC = 2.7 V to 5.5 V * Active mode * Sleep mode
(4)
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used
osc (MHz) 20.0 16.0
2.0 Vcc(V) 3.0 4.5 5.5
Operation guarantee range Operation guarantee range except A/D conversion accuracy
Rev. 4.00 Sep. 23, 2005 Page 269 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.3.2
DC Characteristics
Table 18.10 DC Characteristics (1) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Values Item Symbol Applicable Pins Test Condition Min VCC x 0.8 Typ Max -- VCC + 0.3 Unit V Notes RES, NMI VCC = 4.0 V to 5.5 V WKP0 to WKP5, IRQ0, IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, SCK3_2, 1 SCK3_3* , TRGV RXD, RXD_2, 1 RXD_3* , P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70, P84 to P80 PB3 to PB0 VCC = 4.0 V to 5.5 V
Input high VIH voltage
VCC x 0.9
--
VCC + 0.3
VCC x 0.7
--
VCC + 0.3
V
VCC x 0.8
--
VCC + 0.3
VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V
VCC x 0.7 VCC x 0.8 VCC - 0.5 VCC - 0.3 -0.3
-- -- -- -- --
AVCC + 0.3 V AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.2 V V
OSC1
Input low VIL voltage
RES, NMI VCC = 4.0 V to 5.5 V WKP0 to WKP5, IRQ0, IRQ3, ADTRG,TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, SCK3_2, 1 SCK3_3* , TRGV RXD, RXD_2, 1 RXD_3* , P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70, P84 to P80 PB3 to PB0 OSC1 VCC = 4.0 V to 5.5 V
-0.3
--
VCC x 0.1
-0.3
--
VCC x 0.3
V
-0.3
--
VCC x 0.2
VCC = 4.0 V to 5.5 V
-0.3 -0.3
-- --
0.5 0.3
V
Rev. 4.00 Sep. 23, 2005 Page 270 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Item Output high voltage Symbol VOH Applicable Pins P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70, P84 to P80 P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70 P84 to P80 Test Condition VCC = 4.0 V to 5.5 V -IOH = 1.5 mA -IOH = 0.1 mA VCC - 0.5 -- -- Min Typ Max -- Unit V Notes
VCC - 1.0 --
Output low voltage
VOL
VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA VCC = 4.0 V to 5.5 V IOL = 20.0 mA VCC = 4.0 V to 5.5 V IOL = 10.0 mA VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA
--
--
0.6
V
-- --
-- --
0.4 1.5 V
--
--
1.0
--
--
0.4
-- --
-- --
0.4 1.0 A
Input/ output leakage current
| IIL |
OSC1, RES, VIN = 0.5 V to NMI, WKP0 to (VCC - 0.5 V) WKP5, IRQ0, IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, 1 RXD_2, RXD_3* , SCK3, SCK3_2, 1 SCK3_3* P12 to P10, P17 to P14, P22 to P20, P57 to P50, P76 to P70, P84 to P80 PB3 to PB0 VIN = 0.5 V to (VCC - 0.5 V)
--
--
1.0
A
VIN = 0.5 V to (AVCC - 0.5 V)
--
--
1.0
A
Rev. 4.00 Sep. 23, 2005 Page 271 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Item Pull-up MOS current Symbol -Ip Applicable Pins P12 to P10, P17 to P14, P55 to P50 Test Condition VCC = 5.0 V, VIN = 0.0 V VCC = 3.0 V, VIN = 0.0 V f = 1 MHz, VIN = 0.0 V, Ta = 25C Active mode 1 VCC = 5.0 V, fOSC = 20 MHz Active mode 1 VCC = 3.0 V, fOSC = 10 MHz VCC Active mode 2 VCC = 5.0 V, fOSC = 20 MHz Active mode 2 VCC = 3.0 V, fOSC = 10 MHz ISLEEP1 Sleep mode current consumption VCC Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz VCC Sleep mode 2 VCC = 5.0 V, fOSC = 20 MHz Sleep mode 2 VCC = 3.0 V, fOSC = 10 MHz ISTBY Standby mode current consumption VCC Min 50.0 -- -- Typ -- 60.0 -- Max 300.0 -- 15.0 pF Unit A Reference value Notes
Input capacitance
Cin
All input pins except power supply pins VCC
IOPE1 Active mode current consumption
--
15.0
30.0
mA
*
2
--
8.0
--
* Reference value mA *
2
2
IOPE2
--
1.8
3.0
--
1.2
--
* Reference value mA *
2
2
--
11.5
22.5
--
6.5
--
* Reference value mA *
2
2
ISLEEP2
--
1.7
2.7
--
1.1
--
* Reference value A *
2
2
--
--
5.0
Rev. 4.00 Sep. 23, 2005 Page 272 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Item Symbol Applicable Pins VCC Test Condition Min 2.0 Typ -- Max -- Unit V Notes
RAM data VRAM retaining voltage
Notes: 1. The SCK3_3 and RXD_3 pins are not available in the H8/36014. 2. Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Mode Active mode 1 Active mode 2 Sleep mode 1 Sleep mode 2 Standby mode VCC VCC RES Pin VCC Internal State Operates Operates (OSC/64) Only timers operate Only timers operate (OSC/64) CPU and timers both stop VCC Main clock: ceramic or crystal resonator VCC Other Pins VCC Oscillator Pins Main clock: ceramic or crystal resonator
Rev. 4.00 Sep. 23, 2005 Page 273 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
Table 18.10 DC Characteristics (2) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Item Allowable output low current (per pin) Symbol IOL Pins Output pins except port 8 Port 8 Output pins except port 8 Port 8 Allowable output low current (total) IOL Output pins except port 8 Port 8 Output pins except port 8 Port 8 Allowable output high I -IOH I current (per pin) All output pins VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Test Condition Min VCC = 4.0 V to 5.5 V -- -- -- -- -- -- -- -- -- -- Allowable output high I -IOH I current (total) All output pins VCC = 4.0 V to 5.5 V -- -- Values Typ -- -- -- -- -- -- -- -- -- -- -- -- Max 2.0 20.0 0.5 10.0 40.0 80.0 20.0 40.0 2.0 0.2 30.0 8.0 Unit mA mA mA mA mA mA mA mA mA mA mA mA
Rev. 4.00 Sep. 23, 2005 Page 274 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.3.3
AC Characteristics
Table 18.11 AC Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins OSC1, OSC2 Values Test Condition Min Typ -- -- -- -- -- -- Max 20.0 10.0 64 12.8 -- 10.0 Unit MHz MHz tOSC s tcyc ms *
2
Item System clock oscillation frequency System clock () cycle time Instruction cycle time Oscillation stabilization time (crystal resonator)
Symbol fOSC
Reference Figure *
1
VCC = 4.0 V to 5.5 V 2.0 2.0
tcyc
1 -- 2
trc
OSC1, OSC2 OSC1, OSC2 OSC1
--
trc Oscillation stabilization time (ceramic resonator) External clock high width External clock low width External clock rise time External clock fall time RES pin low width tCPH tCPL tCPr tCPf tREL
--
--
5.0
ms
VCC = 4.0 V to 5.5 V 20.0 40.0 VCC = 4.0 V to 5.5 V 20.0 40.0 VCC = 4.0 V to 5.5 V -- -- VCC = 4.0 V to 5.5 V -- -- At power-on and in trc modes other than those below In active mode and 200 sleep mode operation
-- -- -- -- -- -- -- -- --
-- -- -- -- 10.0 15.0 10.0 15.0 --
ns ns ns ns ns ns ns ns ms
Figure 18.1
OSC1
OSC1
OSC1 RES
Figure 18.2
--
--
ns
Rev. 4.00 Sep. 23, 2005 Page 275 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Test Condition Min 2 Typ -- Max -- Unit tcyc
Item Input pin high width
Symbol tIH
Applicable Pins NMI, IRQ0, IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD NMI, IRQ0, IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD
Reference Figure Figure 18.3
Input pin low width
tIL
2
--
--
tcyc
Notes: 1. When an external clock is input, the minimum system clock oscillator frequency is 1.0 MHz. 2. Determined by the MA2 to MA0 bits in the system control register 2 (SYSCR2).
Rev. 4.00 Sep. 23, 2005 Page 276 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
Table 18.12 Serial Interface (SCI3) Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins SCK3, SCK3_2, SCK3_3* Values Test Condition Min 4 6 Typ Max Unit -- -- -- -- tcyc tcyc Reference Figure Figure 18.4
Item Input clock cycle Asynchronous Clocked synchronous
Symbol tScyc
Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous)
tSCKW
SCK3, SCK3_2, SCK3_3* TXD, TXD_2, TXD_3* RXD, RXD_2, RXD_3* RXD, RXD_2, RXD_3* VCC = 4.0 V to 5.5 V
0.4
--
0.6
tScyc
tTXD
-- --
-- -- -- -- -- --
1 1 -- -- -- --
tcyc tcyc ns ns ns ns
Figure 18.5
tRXS
VCC = 4.0 V to 5.5 V
50.0 100.0
tRXH
VCC = 4.0 V to 5.5 V
50.0 100.0
Note:
*
The SCK3_3, RXD_3, and TXD_3 pins are not available in the H8/36014.
Rev. 4.00 Sep. 23, 2005 Page 277 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.3.4
A/D Converter Characteristics
Table 18.13 A/D Converter Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins AVCC AN3 to AN0 AVCC Test Condition Values Min 3.0 VSS - 0.3 AVCC = 5.0 V -- fOSC = 20 MHz AVCC -- 50 -- A * Reference value *
3 2
Item
Symbol
Typ Max VCC -- -- 5.5
Unit V
Notes *
1
Analog power supply AVCC voltage Analog input voltage AVIN Analog power supply AIOPE current
AVCC + 0.3 V 2.0 mA
AISTOP1
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy CAIN RAIN
AVCC AN3 to AN0 AN3 to AN0
-- -- -- 10 AVCC = 3.0 V 134 to 5.5 V -- -- -- -- -- AVCC = 4.0 V 70 to 5.5 V -- -- -- -- --
-- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- --
5.0 30.0 5.0 10 -- 7.5 7.5 7.5 0.5 8.0 -- 7.5 7.5 7.5 0.5 8.0
A pF k bit tcyc LSB LSB LSB LSB LSB tcyc LSB LSB LSB LSB LSB
Rev. 4.00 Sep. 23, 2005 Page 278 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics Values Min Typ Max -- -- -- -- -- -- -- 3.5 3.5 3.5 0.5 4.0 Unit tcyc LSB LSB LSB LSB LSB
Item Conversion time (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
Symbol
Applicable Pins
Test Condition
Reference Figure
AVCC = 4.0 V 134 to 5.5 V -- -- -- -- --
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby and subsleep modes while the A/D converter is idle.
18.3.5
Watchdog Timer Characteristics
Table 18.14 Watchdog Timer Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified.
Applicable Pins Test Condition Values Min 0.2 Typ 0.4 Max -- Unit s Notes *
Item On-chip oscillator overflow time
Symbol tOVF
Note: * Shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
Rev. 4.00 Sep. 23, 2005 Page 279 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.3.6
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 18.15 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min Typ 3.7 4.0 2.3 3.6 -- -- -- Max -- 4.5 2.7 4.2 -- -- 350 Unit V V V V V s A
Item Power-supply falling detection voltage Power-supply rising detection voltage Reset detection voltage 1*1 Reset detection voltage 2*
2
Symbol Vint (D) Vint (U) Vreset1 Vreset2 VLVDRmin tLVDON ISTBY
LVDSEL = 0 3.3 LVDSEL = 0 -- LVDSEL = 0 -- LVDSEL = 1 3.0 1.0 50 LVDE = 1, Vcc = 5.0 V, When a 32kHz crystal resonator is not used
Lower-limit voltage of LVDR 3 operation* LVD stabilization time Current consumption in standby mode
Notes: 1. This voltage should be used when the falling and rising voltage detection function is used. 2. Select the low-voltage reset 2 when only the low-voltage detection reset is used. 3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset may not occur. Therefore sufficient evaluation is required.
Rev. 4.00 Sep. 23, 2005 Page 280 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
18.3.7
Power-On Reset Circuit Characteristics (Optional)
Table 18.16 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated.
Test Condition Values Min 100 -- Typ 150 -- Max -- 100 Unit k mV
Item Pull-up resistance of RES pin Power-on reset start voltage* Note: *
Symbol RRES Vpor
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely. In order to remove charge of the RES pin, it is recommended that the diode be placed in the Vcc side. If the power-supply voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
18.4
Operation Timing
t OSC
VIH OSC1 VIL
t CPH t CPr
t CPL t CPf
Figure 18.1 System Clock Input Timing
Rev. 4.00 Sep. 23, 2005 Page 281 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
VCC
VCC x 0.7
OSC1
tREL
RES
VIL
VIL tREL
Figure 18.2 RES Low Width Timing
NMI, IRQ0, IRQ3 WKP0 to WKP5 ADTRG FTCI FTIOA to FTIOD TMCIV, TMRIV TRGV
VIH VIL
t IL
t IH
Figure 18.3 Input Timing
t SCKW
SCK3, SCK_2
t Scyc
Figure 18.4 SCK3 Input Clock Timing
Rev. 4.00 Sep. 23, 2005 Page 282 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
t Scyc
VIH or VOH *2 SCK3, SCK3_2, VIL or VOL *2 SCK3_3*1
t TXD
TXD, TXD_2, TXD_3*1 (transmit data)
VOH*2 VOL *2
t RXS
t RXH
RXD, RXD_2, RXD_3*1 (receive data)
Notes: 1. The SCK3_3, RXD_3, and TXD_3 pins are not available in the H8/36014. 2. Output timing reference levels Output high: Output low: V OH= 2.0 V V OL= 0.8 V
Load conditions are shown in figure 18.6.
Figure 18.5 SCI3 Input/Output Timing in Clocked Synchronous Mode
18.5
Output Load Condition
VCC
2.4 k
LSI output pin 30 pF 12 k
Figure 18.6 Output Load Circuit
Rev. 4.00 Sep. 23, 2005 Page 283 of 354 REJ09B0025-0400
Section 18 Electrical Characteristics
Rev. 4.00 Sep. 23, 2005 Page 284 of 354 REJ09B0025-0400
Appendix
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / Description General (destination*) register General (source*) register General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Logical exclusive OR of the operands on both sides NOT (logical complement)
Rev. 4.00 Sep. 23, 2005 Page 285 of 354 REJ09B0025-0400
Appendix
Symbol ( ), < >
Description Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7).
Condition Code Notation
Symbol
Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes
* 0 1 --
Rev. 4.00 Sep. 23, 2005 Page 286 of 354 REJ09B0025-0400
Appendix
Table A.1
Instruction Set
1. Data transfer instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
MOV MOV.B #xx:8, Rd
B B B B B B
2 2 2 4 8 2
---- ---- ---- ---- ---- ----
#xx:8 Rd8 Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 @ERs Rd8 ERs32+1 ERs32 2 4 6 2 4 8 2 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) ERd32-1 ERd32 Rs8 @ERd 2 4 6 Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16 2 2 4 8 2 Rs16 Rd16 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 @ERs Rd16 ERs32+2 @ERd32 4 6 2 4 8 @aa:16 Rd16 @aa:24 Rd16 Rs16 @ERd Rs16 @(d:16, ERd) Rs16 @(d:24, ERd)
0-- 0-- 0-- 0-- 0-- 0--
2 2 4 6 10 6
MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd
MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd
B B B B B B B
---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0--
4 6 8 4 6 10 6
MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd
B B B W4 W W
---- ---- ---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
4 6 8 4 2 4 6 10 6
MOV.W @(d:16, ERs), Rd W MOV.W @(d:24, ERs), Rd W MOV.W @ERs+, Rd W
MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd
W W W
---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0--
6 8 4 6 10
MOV.W Rs, @(d:16, ERd) W MOV.W Rs, @(d:24, ERd) W
Rev. 4.00 Sep. 23, 2005 Page 287 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd
W
2
ERd32-2 ERd32 Rs16 @ERd 4 6 Rs16 @aa:16 Rs16 @aa:24 #xx:32 Rd32 ERs32 ERd32
----
0--
6
W W L L L L L L 6 2 4 6 10 4
---- ---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
6 8 6 2 8 10 14 10
@ERs ERd32 @(d:16, ERs) ERd32 @(d:24, ERs) ERd32 @ERs ERd32 ERs32+4 ERs32 6 8 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd 6 10 4 ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) ERd32-4 ERd32 ERs32 @ERd 6 8 ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP 2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP Cannot be used in this LSI Cannot be used in this LSI
MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd
L L L L L L 4
---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0--
10 12 8 10 14 10
MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP POP.W Rn POP.L ERn
L L W
---- ---- ----
0-- 0-- 0--
10 12 6
L
----
0--
10
PUSH PUSH.W Rn PUSH.L ERn
W
----
0--
6
L
----
0--
10
MOVFPE
MOVFPE @aa:16, Rd
B 4
Cannot be used in this LSI Cannot be used in this LSI
MOVTPE
MOVTPE Rs, @aa:16
B 4
Rev. 4.00 Sep. 23, 2005 Page 288 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
2. Arithmetic instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd
B B
2 2
-- --
Rd8+#xx:8 Rd8 Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16 2 Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32 2 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8 2 2 2 2 2 2 2 2 2 2 Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16 ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16 2 Rd16-Rs16 Rd16
2 2 4 2 6
W4 W L 6
-- (1) -- (1) -- (2)
ADD.L ERs, ERd
L
-- (2)
2
ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC INC.B Rd INC.W #1, Rd INC.W #2, Rd INC.L #1, ERd INC.L #2, ERd DAA SUB DAA Rd
B B L L L B W W L L B
2
-- --
(3) (3)
2 2 2 2 2 2 2 2 2 2 2
------------ ------------ ------------

---- ---- ---- ---- ---- --*
-- -- -- -- --
*--

SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd
B W4 W L L B B L L L B W W 2 6
2
--
2 4 2 6 2 2 2 2 2 2 2 2 2
-- (1) -- (1)
ERd32-#xx:32 ERd32 -- (2) 2 ERd32-ERs32 ERd32 -- (2)
SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd
Rd8-#xx:8-C Rd8 2 2 2 2 2 2 2 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16
-- --
(3) (3)
------------ ------------ ------------

---- ---- ----
-- -- --
Rev. 4.00 Sep. 23, 2005 Page 289 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
DEC DEC.L #1, ERd DEC.L #2, ERd DAS DAS.Rd
L L B
2 2 2
---- ---- --*
ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8 Rd8 x Rs8 Rd16 (unsigned multiplication) Rd16 x Rs16 ERd32 (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8
-- --
2 2 2
*--
MULXU MULXU. B Rs, Rd
B
2
------------
14
MULXU. W Rs, ERd
W
2
------------

22
MULXS MULXS. B Rs, Rd
B
4
----
----
16
MULXS. W Rs, ERd
W
4
----
----
24
DIVXU DIVXU. B Rs, Rd
B
2
-- -- (6) (7) -- --
14
DIVXU. W Rs, ERd
W
2
-- -- (6) (7) -- --
22
DIVXS DIVXS. B Rs, Rd
B
4
-- -- (8) (7) -- --
16
DIVXS. W Rs, ERd
W
4
-- -- (8) (7) -- --
24

CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd
B B
2 2
-- --
2 2 4 2 4 2
Rd8-Rs8 Rd16-#xx:16
W4 W L L 6 2 2
-- (1) -- (1) -- (2) -- (2)
Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32
Rev. 4.00 Sep. 23, 2005 Page 290 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C

NEG NEG.B Rd NEG.W Rd NEG.L ERd EXTU EXTU.W Rd EXTU.L ERd
2 2 2 2
-- -- --
B 0-Rd8 Rd8 W 0-Rd16 Rd16 L 0-ERd32 ERd32 W 0 ( of Rd16) L 0 ( of ERd32) W ( of Rd16) ( of Rd16) L ( of ERd32) ( of ERd32)
2 2 2 2
---- 0
0--
2
---- 0
0--
2
EXTS EXTS.W Rd EXTS.L ERd
2
----
0--
2
2
----
0--
2
Rev. 4.00 Sep. 23, 2005 Page 291 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation
@-ERn/@ERn+
Operand Size
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
3. Logic instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
AND
AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd
B B
2 2
---- ---- ---- ----
Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 2 Rd16Rs16 Rd16
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2
W4 W L L B B W4 W L L B B W4 W L L B W L 6 4 2 2 2 2 2 2 6 4 2 2 2 6 4
ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
OR
OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd
XOR
XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd
ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8 Rd8 Rd16 Rd16 Rd32 Rd32 ---- ---- ----
NOT
NOT.B Rd NOT.W Rd NOT.L ERd
Rev. 4.00 Sep. 23, 2005 Page 292 of 354 REJ09B0025-0400
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
4. Shift instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd
ROTXL ROTXL.B Rd
B W L B W L B W L B W L B W L B W L B W L B W L
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C MSB LSB C MSB C MSB 0 MSB C MSB LSB C MSB C MSB LSB LSB LSB LSB LSB
0
---- ---- ---- ---- ---- ---- ----
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
---- ---- ----
C
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
ROTXL.W Rd ROTXL.L ERd
ROTXR ROTXR.B Rd
ROTXR.W Rd ROTXR.L ERd ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd
C MSB LSB
---- ----
Rev. 4.00 Sep. 23, 2005 Page 293 of 354 REJ09B0025-0400
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
5. Bit manipulation instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT BNOT #xx:3, Rd
B B B B B B B B B B B B B
2 4 4 2 4 4 2 4 4 2 4 4 2
(#xx:3 of Rd8) 1 (#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8) 4 (#xx:3 of @ERd) (#xx:3 of @ERd) 4 (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) 4 (Rn8 of @ERd) (Rn8 of @ERd) 4 (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z 4 4 (#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z 4 4 (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C
------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
2 8 8 2 8 8 2 8 8 2 8 8 2
BNOT #xx:3, @ERd
B
------------
8
BNOT #xx:3, @aa:8
B
------------
8
BNOT Rn, Rd
B
2
------------
2
BNOT Rn, @ERd
B
------------
8
BNOT Rn, @aa:8
B
------------
8
BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD BLD #xx:3, Rd
B B B B B B B
2
------ ------ ------ ------ ------ ------
---- ---- ---- ---- ---- ----
2 6 6 2 6 6 2
2
2
----------
Rev. 4.00 Sep. 23, 2005 Page 294 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
BLD
BLD #xx:3, @ERd BLD #xx:3, @aa:8
B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 2 2 2 2 2 2 2 2
4 4
---------- ---------- ---------- ---------- ----------
(#xx:3 of @ERd) C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd) C 4 (#xx:3 of @aa:8) C C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C 4 C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C 4 C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C
6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6
BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST BST #xx:3, Rd BST #xx:3, @ERd BIST BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND BAND #xx:3, Rd BAND #xx:3, @ERd BIAND BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8
4
------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
4
4
4
4
4
4
4
4 4
C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C ----------
Rev. 4.00 Sep. 23, 2005 Page 295 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation @(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
6. Branching instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
Branch Condition If condition Always is true then PC PC+d Never else next; CZ=0 CZ=1 C=0
I
H
N
Z
V
C
Bcc
BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6
C=1
------------ ------------
Z=0
------------ ------------
Z=1
------------ ------------
V=0
------------ ------------
V=1
------------ ------------
N=0
------------ ------------
N=1
------------ ------------
NV = 0
------------ ------------
NV = 1 Z (NV) = 0 Z (NV) = 1
------------ ------------ ------------ ------------ ------------ ------------
Rev. 4.00 Sep. 23, 2005 Page 296 of 354 REJ09B0025-0400
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
JMP
JMP @ERn JMP @aa:24 JMP @@aa:8
-- -- -- --
2 4 2 2
PC ERn PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC ERn 4 PC @-SP PC aa:24 2 PC @-SP PC @aa:8 2 PC @SP+
------------ ------------ ------------ ------------ 8 6
4 6 10 8
BSR
BSR d:8
BSR d:16 JSR
--
4
------------
8
10
JSR @ERn
--
2
------------
6
JSR @aa:24
--
------------
8
10
JSR @@aa:8
--
------------
8
12
RTS
RTS
--
------------
8
10
Rev. 4.00 Sep. 23, 2005 Page 297 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
8
Appendix
7. System control instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
TRAPA TRAPA #x:2
--
2 PC @-SP CCR @-SP PC CCR @SP+ PC @SP+ Transition to powerdown state 2 2 4 6 10 4 #xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR @ERs CCR ERs32+2 ERs32 6 8 2 4 6 10 4 @aa:16 CCR @aa:24 CCR CCR Rd8 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) ERd32-2 ERd32 CCR @ERd 6 8 2 2 2 CCR @aa:16 CCR @aa:24 CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2
1 -- -- -- -- -- 14
16

RTE
RTE
--
10
SLEEP SLEEP
--
------------

2
LDC
LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR
B B W W W W
2 2 6 8 12 8


LDC @aa:16, CCR LDC @aa:24, CCR STC STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd
W W B W W W W
8 10 2 6 8 12 8
------------ ------------ ------------ ------------ ------------ ------------ ------------

STC CCR, @aa:16 STC CCR, @aa:24 ANDC ANDC #xx:8, CCR ORC
NOP
W W B B B --
8 10 2 2 2 2
ORC #xx:8, CCR
XORC XORC #xx:8, CCR NOP
------------
Rev. 4.00 Sep. 23, 2005 Page 298 of 354 REJ09B0025-0400
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
8. Block transfer instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
EEPMOV
EEPMOV. B
--
4 if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next 4 if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next
-- -- -- -- -- -- 8+ 4n*2
EEPMOV. W
--
-- -- -- -- -- -- 8+ 4n*2
Notes: 1. The number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. For other cases see Appendix A.3, Number of Execution States. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev. 4.00 Sep. 23, 2005 Page 299 of 354 REJ09B0025-0400
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
A.2
Appendix
Table A.2
Instruction code: Instruction when most significant bit of BH is 1.
4 ORC ADD SUB Table A-2 Table A-2 (2) (2) CMP SUBX OR.B XOR.B AND.B Table A-2 (2) XORC ANDC LDC Table A-2 Table A-2 (2) (2) MOV ADDX 5 6 7 8 9 A B C D E F Table A-2 (2) Table A-2 (2)
REJ09B0025-0400
1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0.
3 LDC
AL
AH
0
1
2
0
NOP
Table A-2 (2)
STC
1
Table A-2 Table A-2 Table A-2 Table A-2 (2) (2) (2) (2)
2 MOV.B
Operation Code Map
Rev. 4.00 Sep. 23, 2005 Page 300 of 354
Operation Code Map (1)
3 BLS DIVXU BST OR BTST BOR MOV BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD BXOR BAND BIST BLD XOR AND RTS BSR RTE TRAPA Table A-2 (2) JMP MOV Table A-2 Table A-2 EEPMOV (2) (2) Table A-2 (3) BCC BCS BNE BEQ BVC BVS BPL BMI BGE BSR BLT BGT JSR BLE
4
BRA
BRN
BHI
5
MULXU
DIVXU
MULXU
6
BSET
BNOT
BCLR
7
8
9
A
B
C
D
E
F
Table A.2
Instruction code:
1st byte 2nd byte AH AL BH BL
2 LDC/STC
ADD
INC
ADDS
BH AH AL 3 SLEEP
Table A-2 Table A-2 (3) (3)
0
1
4
5
6
7
8
9
A
B
C
D
E
F Table A-2 (3)
01
MOV
0A
INC
INC
0B
MOV
SHLL
SHAL SHAR ROTL ROTR SHAL SHAR ROTL ROTR NEG NEG
ADDS
INC
INC
Operation Code Map (2)
0F
DAA
10
SHLR ROTXL ROTXR NOT EXTU EXTU
SHLL
11
SHLR
12
ROTXL
13
ROTXR
17
NOT
EXTS
EXTS
1A
DEC DEC
DEC
SUB
SUB
DEC DEC
1B
SUBS
1F BHI CMP CMP
SUB SUB BLS
DAS BCC OR OR
XOR XOR BCS BNE AND AND BEQ
CMP
58
BRA
BRN
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
79
MOV
ADD
7A
MOV
ADD
Appendix
Rev. 4.00 Sep. 23, 2005 Page 301 of 354
REJ09B0025-0400
Appendix
Table A.2
REJ09B0025-0400
Instruction code:
1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL
Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1.
CL 2 3 4 5 6 7 8 9 A B C D E F
AH ALBH BLCH
LDC STC STC LDC LDC STC
0
1
01406 MULXS DIVXS OR BTST
BOR BXOR BIXOR
BIST
LDC STC
Rev. 4.00 Sep. 23, 2005 Page 302 of 354
Operation Code Map (3)
01C05
MULXS
01D05 XOR AND
DIVXS
01F06
7Cr06 * 1
BAND BIAND BILD BST BLD
7Cr07 * 1 BTST
BIOR
7Dr06 * 1 BCLR BCLR BTST BOR BTST BIOR BCLR
BIST
BSET
BNOT
7Dr07 * 1
BSET
BNOT
7Eaa6 * 2 BXOR BIXOR BIAND BAND BLD
7Eaa7 * 2
7Faa6 * 2 BCLR
BILD BST
BSET
BNOT
7Faa7 * 2
BSET
BNOT
Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression:
Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8
L=M=N=0
Rev. 4.00 Sep. 23, 2005 Page 303 of 354 REJ09B0025-0400
Appendix
Table A.3
Number of Cycles in Each Instruction
Access Location On-Chip Memory SI SJ SK SL SM SN 2 or 3* 2 or 3* 1 2 On-Chip Peripheral Module --
Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: *
Depends on which on-chip peripheral module is accessed. See section 17.1, Register Addresses (Address Order).
Rev. 4.00 Sep. 23, 2005 Page 304 of 354 REJ09B0025-0400
Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction Fetch I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDX ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8
Rev. 4.00 Sep. 23, 2005 Page 305 of 354 REJ09B0025-0400
Appendix
Instruction Instruction Mnemonic Bcc BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 Fetch I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2
2 2
1 1
1 1
Rev. 4.00 Sep. 23, 2005 Page 306 of 354 REJ09B0025-0400
Appendix
Instruction Fetch Instruction Mnemonic BIOR BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR BSR d:8 BSR d:16 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 1 2 2
Branch J
Stack K
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation
1 1
2 2
1 1
1 1
2 2
2 2
1 1
2 2
2 2 1 1 2
2 2
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Appendix
Instruction Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DUVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd Fetch I 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
1 1
1 1
1 1
12 20 12 20 2n+2*
1
2n+2*1
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Appendix
Instruction Instruction Mnemonic INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR LDC@(d:24,ERs), CCR LDC@ERs+, CCR LDC@aa:16, CCR LDC@aa:24, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @Erd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8 Fetch I 1 1 1 2 2 2 2 2 2 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
2 1 1 1 1 1 2 2
1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 1 2 2
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Appendix
Instruction Instruction Mnemonic MOV MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16,ERd) MOV.W Rs, @(d:24,ERd) MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16,ERs), ERd MOV.L @(d:24,ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs,@ERd MOV.L ERs, @(d:16,ERd) MOV.L ERs, @(d:24,ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 MOVFPE MOVTPE MOVFPE @aa:16, Rd* MOVTPE Rs,@aa:16*
2 2
Branch
Stack
Byte Data Access L 1 1
Word Data Access M
Internal Operation N
Fetch I 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 2
Addr. Read Operation J K
1 1 1 1 1 1 1 1 1 1 1 1 2 2
2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2
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Appendix
Instruction Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC POP ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd Fetch I 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N 12 20 12 20
Addr. Read Operation J K
1 2 1 2
2 2 2 2
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Appendix
Instruction Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC SLEEP STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16,ERd) STC CCR, @(d:24,ERd) STC CCR,@-ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS SUBS #1/2/4, ERd Fetch I 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 5 2 3 4 1 2 1 3 1 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
2 1
2 2
1 1 1 1 1 1 2
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Appendix
Instruction Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd TRAPA XOR TRAPA #xx:2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR Fetch I 1 1 2 1 1 2 1 3 2 1
Branch
Stack
Byte Data Access L
Word Data Access M
Internal Operation N
Addr. Read Operation J K
1
2
4
Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2. Cannot be used in this LSI.
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Appendix
A.4
Combinations of Instructions and Addressing Modes
Combinations of Instructions and Addressing Modes
Addressing Mode
@ERn+/@ERn @(d:16.ERn) @(d:24.ERn) @(d:16.PC)
Table A.5
@@aa:8
Functions
Instructions
@ERn #xx
@(d:8.PC)
@aa:16
@aa:24
@aa:8
Rn
Data MOV transfer POP, PUSH instructions MOVFPE, MOVTPE Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS AND, OR, XOR
BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- BWL BWL WL BWL B B -- -- -- -- L BWL B BW -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
B -- -- -- -- -- -- -- -- --
BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- WL -- -- -- -- -- -- -- --
Logical operations
-- -- -- -- -- -- -- -- -- -- -- -- B -- B -- --
BWL WL BWL BWL BWL B -- -- -- -- -- -- B B -- -- --
-- -- -- -- -- B -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
NOT Shift operations Bit manipulations Branching BCC, BSR instructions JMP, JSR RTS System TRAPA control RTE instructions SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer instructions
-- --
BW
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--
Appendix
Appendix B I/O Port Block Diagrams
B.1 I/O Port Block Diagrams
RES goes low in a reset, and SBY goes low in a reset and in standby mode.
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ TRGV Legend PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.1 Port 1 Block Diagram (P17)
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Appendix
Internal data bus
RES PUCR
SBY
Pull-up MOS PMR
PDR
PCR
IRQ Legend PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.2 Port 1 Block Diagram (P14)
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Appendix
Internal data bus
RES PUCR
SBY
Pull-up MOS
PDR
PCR
Legend PUCR: Port pull-up control register PDR: Port data register PCR: Port control register
Figure B.3 Port 1 Block Diagram (P16, P15, P12*, P10) Note: * This pin is available only in the H8/36014.
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Appendix
SCI3_3
Internal data bus RES PUCR SBY
SCKIE SCKOE
Pull-up MOS
PDR
PCR
SCKO SCKI Legend PUCR: Port pull-up control register PDR: Port data register PCR: Port control register
Figure B.4 Port 1 Block Diagram (P12) (H8/36024)
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Appendix
Internal data bus
RES PUCR
SBY
Pull-up MOS
PDR
PCR
Legend PUCR: Port pull-up control register PDR: Port data register PCR: Port control register
Figure B.5 Port 1 Block Diagram (P11)
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Appendix
Internal data bus
SBY
PMR
PDR
PCR
SCI3 TXD Legend PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.6 Port 2 Block Diagram (P22)
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Appendix
Internal data bus
SBY
PDR
PCR
SCI3 RE RXD Legend PDR: Port data register PCR: Port control register
Figure B.7 Port 2 Block Diagram (P21)
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Appendix
SBY SCI3 SCKIE SCKOE Internal data bus PDR
PCR
SCKO SCKI Legend PDR: Port data register PCR: Port control register
Figure B.8 Port 2 Block Diagram (P20)
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Appendix
Internal data bus
SBY
PMOS
PMR
PDR
PCR
Legend PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.9 Port 5 Block Diagram (P57, P56) (H8/36014)
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Appendix
Internal data bus
SBY
PMOS PMR
PDR
PCR
SCI3_3 TXD_3 Legend PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.10 Port 5 Block Diagram (P57) (H8/36024)
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Appendix
Internal data bus
SBY
PMOS PMR
PDR
PCR
SCI3_3 RE RXD_2 Legend PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.11 Port 5 Block Diagram (P56) (H8/36024)
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Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
ADTRG
Legend PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.12 Port 5 Block Diagram (P55)
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Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
Legend PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.13 Port 5 Block Diagram (P54 to P50)
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Appendix
Internal data bus SBY
Timer V OS3 OS2 OS1 OS0 PDR
PCR
TMOV Legend PDR: Port data register PCR: Port control register
Figure B.14 Port 7 Block Diagram (P76)
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Appendix
Internal data bus
SBY
PDR
PCR
Timer V TMCIV Legend PDR: Port data register PCR: Port control register
Figure B.15 Port 7 Block Diagram (P75)
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Appendix
Internal data bus
SBY
PDR
PCR
Timer V TMRIV Legend PDR: Port data register PCR: Port control register
Figure B.16 Port 7 Block Diagram (P74)
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Appendix
Internal data bus
SBY
PDR
PCR
Legend PDR: Port data register PCR: Port control register
Figure B.17 Port 7 Block Diagram (P73)
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Appendix
Internal data bus
SBY
PMR
PDR
PCR
SCI3_2 TXD_2 Legend PMR: Port mode register PDR: Port data register PCR: Port control register
Figure B.18 Port 7 Block Diagram (P72)
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Appendix
Internal data bus
SBY
PDR
PCR
SCI3_2 RE RXD_2 Legend PDR: Port data register PCR: Port control register
Figure B.19 Port 7 Block Diagram (P71)
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Appendix
SBY SCI3_2 SCKIE SCKOE Internal data bus PDR
PCR
SCKO SCKI Legend PDR: Port data register PCR: Port control register
Figure B.20 Port 7 Block Diagram (P70)
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Appendix
Internal data bus
SBY
Timer W Output control signals A to D PDR
PCR
FTIOA FTIOB FTIOC FTIOD
Legend PDR: Port data register PCR: Port control register
Figure B.21 Port 8 Block Diagram (P84 to P81)
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Appendix
Internal data bus
SBY
PDR
PCR
Timer W FTCI Legend PDR: Port data register PCR: Port control register
Figure B.22 Port 8 Block Diagram (P80)
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Appendix
Internal data bus
A/D converter
DEC
CH3 to CH0 VIN
Figure B.23 Port B Block Diagram (PB3 to PB0)
B.2
Port
Port States in Each Operating State
Reset High impedance High impedance High impedance High impedance High impedance High impedance Active Functioning Functioning Functioning Functioning Functioning High impedance Sleep Retained Retained Retained Retained Retained High impedance Subsleep Retained Retained Retained Retained Retained Retained Standby High impedance* High impedance High impedance* High impedance High impedance High impedance
P17 to P14, P12 to P10 P22 to P20 P57 to P50 P76 to P70 P84 to P80 PB3 to PB0
Note: * High level output when the pull-up MOS is in on state.
Rev. 4.00 Sep. 23, 2005 Page 337 of 354 REJ09B0025-0400
Appendix
Appendix C Product Code Lineup
Product Type H8/36024 Product Code Model Marking
HD64F36024FP HD64F36024FX HD64F36024FY HD64F36024FT HD64F36024GFP HD64F36024GFX HD64F36024GFY HD64F36024GFT HD64336024(***)FP HD64336024(***)FX HD64336024(***)FY HD64336024(***)FT
Package Code
LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
Flash memory Standard HD64F36024FP version product HD64F36024FX
HD64F36024FY HD64F36024FT
Product HD64F36024GFP with POR HD64F36024GFX & LVDC
HD64F36024GFY HD64F36024GFT
Masked ROM Standard HD64336024FP version product HD64336024FX
HD64336024FY HD64336024FT
Product HD64336024GFP with POR HD64336024GFX & LVDC
HD64336024GFY HD64336024GFT
HD64336024G(***)FP LQFP-64 (FP-64E) HD64336024G(***)FX LQFP-48 (FP-48F) HD64336024G(***)FY LQFP-48 (FP-48B) HD64336024G(***)FT QFN-48(TNP-48) HD64336023(***)FP HD64336023(***)FX HD64336023(***)FY HD64336023(***)FT LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
H8/36023
Masked ROM Standard HD64336023FP version product
HD64336023FX HD64336023FY HD64336023FT HD64336023GFP Product with POR HD64336023GFX & LVDC HD64336023GFY HD64336023GFT
HD64336023G(***)FP LQFP-64 (FP-64E) HD64336023G(***)FX LQFP-48 (FP-48F) HD64336023G(***)FY LQFP-48 (FP-48B) HD64336023G(***)FT QFN-48(TNP-48)
Rev. 4.00 Sep. 23, 2005 Page 338 of 354 REJ09B0025-0400
Appendix
Product Type H8/36022
Product Code
Model Marking
HD64F36022FP HD64F36022FX HD64F36022FY HD64F36022FT HD64F36022GFP HD64F36022GFX HD64F36022GFY HD64F36022GFT HD64336022(***)FP HD64336022(***)FX HD64336022(***)FY HD64336022(***)FT
Package Code
LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
Flash memory Standard HD64F36022FP version product HD64F36022FX
HD64F36022FY HD64F36022FT
Product HD64F36022GFP with POR HD64F36022GFX & LVDC
HD64F36022GFY HD64F36022GFT
Masked ROM Standard HD64336022FP product version HD64336022FX
HD64336022FY HD64336022FT
Product HD64336022GFP with POR HD64336022GFX & LVDC
HD64336022GFY HD64336022GFT
HD64336022G(***)FP LQFP-64 (FP-64E) HD64336022G(***)FX LQFP-48 (FP-48F) HD64336022G(***)FY LQFP-48 (FP-48B) HD64336022G(***)FT QFN-48(TNP-48) HD64F36014FP HD64F36014FX HD64F36014FY HD64F36014FT HD64F36014GFP HD64F36014GFX HD64F36014GFY HD64F36014GFT HD64336014(***)FP HD64336014(***)FX HD64336014(***)FY HD64336014(***)FT LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
H8/36014
Flash memory Standard HD64F36014FP version product HD64F36014FX
HD64F36014FY HD64F36014FT
Product HD64F36014GFP with POR HD64F36014GFX & LVDC
HD64F36014GFY HD64F36014GFT
Masked ROM Standard HD64336014FP product version
HD64336014FX HD64336014FY HD64336014FT
Product HD64336014GFP with POR HD64336014GFX & LVDC
HD64336014GFY HD64336014GFT
HD64336014G(***)FP LQFP-64 (FP-64E) HD64336014G(***)FX LQFP-48 (FP-48F) HD64336014G(***)FY LQFP-48 (FP-48B) HD64336014G(***)FT QFN-48(TNP-48)
Rev. 4.00 Sep. 23, 2005 Page 339 of 354 REJ09B0025-0400
Appendix
Product Type H8/36013
Product Code
Model Marking
HD64336013(***)FP HD64336013(***)FX HD64336013(***)FY HD64336013(***)FT
Package Code
LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
Masked ROM Standard HD64336013FP version product HD64336013FX
HD64336013FY HD64336013FT
Product HD64336013GFP with POR HD64336013GFX & LVDC
HD64336013GFY HD64336013GFT
HD64336013G(***)FP LQFP-64 (FP-64E) HD64336013G(***)FX LQFP-48 (FP-48F) HD64336013G(***)FY LQFP-48 (FP-48B) HD64336013G(***)FT QFN-48(TNP-48) HD64F36012FP HD64F36012FX HD64F36012FY HD64F36012FT HD64F36012GFP HD64F36012GFX HD64F36012GFY HD64F36012GFT HD64336012(***)FP HD64336012(***)FX HD64336012(***)FY HD64336012(***)FT LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48) LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
H8/36012
Flash memory Standard HD64F36012FP product version HD64F36012FX
HD64F36012FY HD64F36012FT
Product HD64F36012GFP with POR HD64F36012GFX & LVDC
HD64F36012GFY HD64F36012GFT
Masked ROM Standard HD64336012FP version product HD64336012FX
HD64336012FY HD64336012FT
Product HD64336012GFP with POR HD64336012GFX & LVDC
HD64336012GFY HD64336012GFT
HD64336012G(***)FP LQFP-64 (FP-64E) HD64336012G(***)FX LQFP-48 (FP-48F) HD64336012G(***)FY LQFP-48 (FP-48B) HD64336012G(***)FT QFN-48(TNP-48) HD64336011(***)FP HD64336011(***)FX HD64336011(***)FY HD64336011(***)FT LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
H8/36011
Masked ROM Standard HD64336011FP version product
HD64336011FX HD64336011FY HD64336011FT
Product HD64336011GFP with POR HD64336011GFX & LVDC
HD64336011GFY HD64336011GFT
HD64336011G(***)FP LQFP-64 (FP-64E) HD64336011G(***)FX LQFP-48 (FP-48F) HD64336011G(***)FY LQFP-48 (FP-48B) HD64336011G(***)FT QFN-48(TNP-48)
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Appendix
Product Type H8/36010
Product Code
Model Marking
HD64336010(***)FP HD64336010(***)FX HD64336010(***)FY HD64336010(***)FT
Package Code
LQFP-64 (FP-64E) LQFP-48 (FP-48F) LQFP-48 (FP-48B) QFN-48(TNP-48)
Masked ROM Standard HD64336010FP product version HD64336010FX
HD64336010FY HD64336010FT
Product HD64336010GFP with POR HD64336010GFX & LVDC
HD64336010GFY HD64336010GFT
HD64336010G(***)FP LQFP-64 (FP-64E) HD64336010G(***)FX LQFP-48 (FP-48F) HD64336010G(***)FY LQFP-48 (FP-48B) HD64336010G(***)FT QFN-48(TNP-48)
Legend POR & LVDC: Power-on reset and low-voltage detection circuits (***): ROM code
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Appendix
Appendix D Package Dimensions
The package dimensions that are shows in the Renesas Semiconductor Packages Data Book have priority.
Rev. 4.00 Sep. 23, 2005 Page 342 of 354 REJ09B0025-0400
JEITA Package Code P-LQFP64-10x10-0.50
RENESAS Code PLQP0064KC-A
Previous Code FP-64E/FP-64EV
MASS[Typ.] 0.4g
HD
*1
D
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
48
33
49
bp
b1
32
Reference Symbol
Dimension in Millimeters Min
c1
Nom
c
Max
D E A2
10 10 1.45
E
*2
HE
Terminal cross section
17
ZE
HD
11.8 HE
A A1 0.00 bp b1 0.17 11.8
12.0
12.0
12.2
12.2 1.70 0.10 0.22 0.20 c 0.12 0.17 0.22 0.20 0.27
64
1 Index mark
16
ZD
A
A2
c
A1
Figure D.1 FP-64E Package Dimensions
F
L
c1
0.15
L1
e
x
0 0.5
8
0.08
e
*3
Detail F
bp
y ZD ZE 1.25 1.25
0.10
x
M
y
L
L1
0.3
0.5 1.0
0.7
Appendix
Rev. 4.00 Sep. 23, 2005 Page 343 of 354
REJ09B0025-0400
Appendix
E
*2
HE
c1
c
ZE
A
A2
c
A1
REJ09B0025-0400
RENESAS Code PLQP0048JA-A MASS[Typ.] 0.4g Previous Code FP-48F/FP-48FV
HD
*1
JEITA Package Code P-LQFP48-10x10-0.65
D
36
25
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Rev. 4.00 Sep. 23, 2005 Page 344 of 354
24
bp
b1
37
48
13
Reference Symbol
Dimension in Millimeters Min Nom Max
Terminal cross section
D E
10 10 A2 HD 11.8
HE
1 Index mark F
12
1.45 12.0 11.8 A A1 bp 0.05 0.27 0.1 0.32 12.0 12.2 12.2 1.70 0.15 0.37
Figure D.2 FP-48F Package Dimensions
L
*3
ZD
bp
L1
b1 c c1 0.12
0.30 0.17 0.15 0.22
e
x y M
Detail F
e x y ZD ZE
L
0 0.65
8
0.13 0.10 1.425 1.425 0.4 L1 0.5 1.0 0.6
JEITA Package Code P-LQFP48-7x7-0.50 MASS[Typ.] 0.2g
RENESAS Code PLQP0048KC-A
Previous Code FP-48B/FP-48BV
HD
*1
D
36
25
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
37
24
bp
E
*2
HE
b1
c1
c
ZE
48
13
Reference Symbol
Dimension in Millimeters Min Nom Max
Terminal cross section
D E A2 HD 8.8
7 7 1.40 9.0 9.2
1
12
ZD
F
HE
A A1
8.8
9.0
9.2 1.70 0.03 0.10 0.17
A
A2
c
A1
Figure D.3 FP-48B Package Dimensions
L
L1
*3
bp
0.17
0.22
0.27
b1 c c1 0.12
0.20 0.17 0.15 0.22
e
bp
x y
M
Detail F
e
x y ZD ZE
0 0.5
8
0.08 0.08 0.75 0.75
Appendix
Rev. 4.00 Sep. 23, 2005 Page 345 of 354
REJ09B0025-0400
L
L1
0.4
0.5 1.0
0.6
Appendix
HE
E
ZE
x4 t
ZD
b b1
xM
Lp
c c1
A2
A
A1
Rev. 4.00 Sep. 23, 2005 Page 346 of 354
RENESAS Code PVQN0048KA-A Previous Code TNP-48/TNP-48V MASS[Typ.] 0.1g
HD D
37 24
e
REJ09B0025-0400
25
Reference Symbol
JEITA Package Code P-VQFN48-7x7-0.50
36
Dimension in Millimeters Min D Nom 7.0 E A2 A A1 0.005 b b e L x
p 1
48 13 12
Max
1
7.0 0.90 1.00 0.02 0.17 0.22 0.20 0.5 0.23 0.35 0.47 0.05 y y t
HD HE
1
0.04 0.27
Figure D.4 TNP-48 Package Dimensions
y1 y
0.05 0.20 0.20 7.2 7.2 Z Z
c c
1
D E
0.75 0.75 0.12 0.17 0.15 0.22
Main Revisions and Additions in this Edition
Item Preface Page Revision (See Manual for Details) vi, vii When using the on-chip emulator (E7, E8) for H8/36014 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user. 4. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 5. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode). 6. Use channel 1 of the SCI3 (P21/RXD, P22/TXD) in onboard programming mode by boot mode. Note has been deleted. Section 1 Overview 1.2 Internal Block Diagram Figure 1.1 Internal Block Diagram Figure 1.2 Pin Arrangement (FP-64E) 4 2 2 Can also be used for the E7 or E8 emulator. Can also be used for the E7 or E8 emulator. 3 3 Can also be used for the E7 or E8 emulator.
Figure 1.3 Pin 5 Arrangement (FP-48F, FP48B, TNP-48) Table 1.1 Pin Functions 7
Type E10T
Functions Interface pin for the E10T, E8, or E7 emulator
Section 7 ROM
77
The features of the 32-kbyte (4 kbytes of them are the control program area for E7 or E8) flash memory built into the HD64F36024 and HD64F36014 are summarized below. Note: When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed.
Section 8 RAM
93
Rev. 4.00 Sep. 23, 2005 Page 347 of 354 REJ09B0025-0400
Item Section 12 Watchdog Timer 12.2.1 Timer Control/Status Register WD (TCSRWD)
Page Revision (See Manual for Details) 168 Bit 4 Bit Name TCSRWE Description Timer Control/Status Register WD Write Enable
Section 14 A/D Converter 14.3.1 A/D Data Registers A to D (ADDRA to ADDRD) Section 18 Electrical Characteristics Table 18.2 DC Characteristics (1)
220
Therefore byte access to ADDR should be done by reading the upper byte first then the lower one. Word access is also possible. ADDR is initialized to H'0000.
254
Values Item Symbol Applicable Pins PB3 to PB0 Test Condition VCC = 4.0 V to 5.5 V Min VCC x 0.7 VCC x 0.8 RXD, RXD_2, RXD_3*1, P12 to P10, P17 to P14, : PB3 to PB0 VCC = 4.0 V to 5.5 V -0.3
Input high VIH voltage Input low voltage VIL
Table 18.2 DC Characteristics (1)
257
Mode Active mode 1 Active mode 2 Sleep mode 1 Sleep mode 2 VCC RES Pin VCC Internal State Operates Operates (OSC/64) Only timers operate Only timers operate (OSC/64)
Rev. 4.00 Sep. 23, 2005 Page 348 of 354 REJ09B0025-0400
Item Table 18.10 DC Characteristics (1)
Page Revision (See Manual for Details) 270
Values Item Symbol Applicable Pins PB3 to PB0 Test Condition VCC = 4.0 V to 5.5 V Min VCC x 0.7 VCC x 0.8 RXD, RXD_2, RXD_3*1, P12 to P10, P17 to P14, : PB3 to PB0 VCC = 4.0 V to 5.5 V -0.3
Input high VIH voltage Input low voltage VIL
Table 18.10 DC Characteristics (1)
273
Mode Active mode 1 Active mode 2 Sleep mode 1 Sleep mode 2 VCC RES Pin VCC Internal State Operates Operates (OSC/64) Only timers operate Only timers operate (OSC/64)
Appendix D Package Dimensions Figure D.1 FP-64E Package Dimensions Figure D.2 FP-48F Package Dimensions Figure D.3 FP-48B Package Dimensions Figure D.4 TNP-48 Package Dimensions
343
Swapped with new one.
344 345 346
Swapped with new one. Swapped with new one. Swapped with new one.
Rev. 4.00 Sep. 23, 2005 Page 349 of 354 REJ09B0025-0400
Rev. 4.00 Sep. 23, 2005 Page 350 of 354 REJ09B0025-0400
Index
A
A/D converter ......................................... 217 A/D conversion time........................... 224 External trigger input.......................... 225 Sample-and-hold circuit...................... 224 Scan mode........................................... 223 Single mode ........................................ 223 Absolute maximum ratings..................... 251 Address break ........................................... 59 Addressing modes..................................... 30 Absolute address................................... 31 Immediate ............................................. 32 Memory indirect ................................... 32 Program-counter relative ...................... 32 Register direct....................................... 31 Register indirect.................................... 31 Register indirect with displacement...... 31 Register indirect with post-increment... 31 Register indirect with pre-decrement.... 31 Trap instruction..................................... 45
F
Flash memory ........................................... 77 Boot mode............................................. 82 Boot program ........................................ 82 Erase/erase-verify ................................. 88 Erasing units ......................................... 78 Error protection..................................... 91 Hardware protection.............................. 91 Program/program-verify ....................... 86 Programming units................................ 78 Programming/erasing in user program mode...................................................... 85 Software protection............................... 91
G
General registers ....................................... 13
C
Clock pulse generators.............................. 65 Condition field.......................................... 28 Condition-code register (CCR)................. 14 CPU ............................................................ 9
I
I/O ports .................................................... 95 I/O port block diagrams ...................... 315 Instruction set............................................ 19 Arithmetic operations instructions ........ 21 Bit Manipulation instructions................ 24 Block data transfer instructions............. 28 Branch instructions ............................... 26 Data Transfer instructions..................... 20 Logic Operations instructions ............... 22 Shift Instructions................................... 23 System control instructions................... 27 Internal power supply step-down circuit ...................................................... 237
E
Effective address....................................... 33 Effective address extension ...................... 28 Electrical characteristics AC Characteristics .............................. 259 DC Characteristics .............................. 254 Exception handling ................................... 45 Reset exception handling...................... 52 Stack status ........................................... 56
Rev. 4.00 Sep. 23, 2005 Page 351 of 354 REJ09B0025-0400
Interrupt Internal interrupts ................................. 54 Interrupt response time ......................... 56 IRQ3 to IRQ0 interrupts ....................... 53 NMI interrupt........................................ 53 WKP5 to WKP0 interrupts ................... 53
Prescaler S ................................................ 67 Product code lineup ................................ 338 Program counter (PC) ............................... 14 PWM operation....................................... 153
R
Register field............................................. 28 Registers ABRKCR...................... 60, 228, 232, 234 ABRKSR ...................... 61, 228, 232, 234 ADCR ......................... 222, 227, 231, 234 ADCSR ....................... 221, 227, 231, 234 ADDRA ...................... 220, 227, 231, 234 ADDRB ...................... 220, 227, 231, 234 ADDRC ...................... 220, 227, 231, 234 ADDRD ...................... 220, 227, 231, 234 BARH ........................... 62, 228, 232, 234 BARL............................ 62, 228, 232, 234 BDRH ........................... 62, 228, 232, 234 BDRL............................ 62, 228, 232, 234 BRR ............................ 184, 227, 231, 234 EBR1............................. 81, 227, 231, 233 FENR ............................ 81, 227, 231, 233 FLMCR1....................... 79, 227, 231, 233 FLMCR2....................... 80, 227, 231, 233 GRA............................ 147, 226, 230, 233 GRB ............................ 147, 227, 230, 233 GRC ............................ 147, 227, 231, 233 GRD............................ 147, 227, 231, 233 IEGR1 ........................... 47, 228, 232, 235 IEGR2 ........................... 48, 229, 232, 235 IENR1 ........................... 49, 229, 232, 235 IRR1.............................. 50, 229, 232, 235 IWPR ............................ 51, 229, 232, 235 LVDCR....................... 231, 226, 230, 233 LVDSR ....................... 232, 226, 230, 233 MSTCR1....................... 72, 229, 232, 235 MSTCR2....................... 72, 229, 232, 235 PCR1............................. 97, 228, 232, 235 PCR2........................... 100, 228, 232, 235 PCR5........................... 104, 228, 232, 235
L
Large current ports...................................... 2 Low-voltage detection circuit ................. 229 LVDI ...................................................... 235 LVDI (interrupt by low voltage detect) circuit...................................................... 235 LVDR ..................................................... 234 LVDR (reset by low voltage detect) circuit...................................................... 234
M
Memory map ............................................ 10 Module standby function .......................... 76
O
On-board programming modes................. 82 Operation field.......................................... 28
P
Package....................................................... 2 Package dimensions................................ 342 Pin arrangement.......................................... 4 Power-down modes .................................. 69 Sleep mode ........................................... 75 Standby mode ....................................... 75 Subsleep mode...................................... 75 Power-on reset ........................................ 229 Power-on reset circuit............................. 233
Rev. 4.00 Sep. 23, 2005 Page 352 of 354 REJ09B0025-0400
PCR7........................... 109, 228, 232, 235 PCR8........................... 112, 228, 232, 235 PDR1 ............................ 97, 228, 232, 234 PDR2 .......................... 101, 228, 232, 234 PDR5 .......................... 105, 228, 232, 234 PDR7 .......................... 109, 228, 232, 234 PDR8 .......................... 113, 228, 232, 235 PDRB.......................... 116, 228, 232, 235 PMR1............................ 96, 228, 232, 235 PMR5.......................... 103, 228, 232, 235 PUCR1.......................... 98, 228, 232, 234 PUCR5........................ 105, 228, 232, 234 RDR............................ 178, 227, 231, 234 RSR..................................................... 178 SCR3........................... 180, 227, 231, 234 SMCR ......................... 191, 226, 230, 233 SMR............................ 179, 227, 231, 234 SSR ............................. 182, 227, 231, 234 SYSCR1 ....................... 70, 228, 232, 235 SYSCR2 ....................... 71, 228, 232, 235 TCNT.......................... 147, 226, 230, 233 TCNTV....................... 119, 227, 231, 234 TCORA....................... 120, 227, 231, 234 TCORB....................... 120, 227, 231, 234 TCRV0 ....................... 121, 227, 231, 234 TCRV1 ....................... 125, 227, 231, 234 TCRW......................... 140, 226, 230, 233 TCSRV ....................... 123, 227, 231, 234 TCSRWD.................... 168, 227, 231, 234 TCWD ........................ 169, 227, 231, 234 TDR ............................ 178, 227, 231, 234 TIERW ....................... 141, 226, 230, 233 TIOR0......................... 144, 226, 230, 233 TIOR1......................... 145, 226, 230, 233
TMRW ........................ 139, 226, 230, 233 TMWD........................ 170, 228, 231, 234 TSR ..................................................... 178 TSRW ......................... 142, 226, 230, 233
S
Serial communication interface 3 (SCI3) 173 Asynchronous mode............................ 192 Bit rate................................................. 184 Break................................................... 215 Clocked synchronous mode ................ 200 Framing error ...................................... 196 Mark state ........................................... 215 Multiprocessor communication function ............................................... 207 Overrun error ...................................... 196 Parity error .......................................... 196 Stack pointer (SP) ..................................... 13 System clocks ........................................... 65
T
Timer V................................................... 117 Timer W.................................................. 135
V
Vector address........................................... 45
W
Watchdog timer....................................... 167
Rev. 4.00 Sep. 23, 2005 Page 353 of 354 REJ09B0025-0400
Rev. 4.00 Sep. 23, 2005 Page 354 of 354 REJ09B0025-0400
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36024 Group, H8/36014 Group
Publication Date: 1st Edition, Mar., 2001 Rev.4.00, Sep. 23, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 3.0
H8/36024 Group, H8/36014 Group Hardware Manual


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